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/linux-6.12.1/Documentation/devicetree/bindings/pps/
Dpps-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pps/pps-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
14 const: pps-gpio
20 echo-gpios:
24 echo-active-ms:
27 assert-falling-edge:
28 description: Indicates a falling edge assert, when present. Rising edge if absent.
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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Drealtek,rtd-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/realtek,rtd-gpio.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Tzuyi Chang <tychang@realtek.com>
15 RTD series SoC family, which are high-definition media processor SoCs.
20 - realtek,rtd1295-misc-gpio
21 - realtek,rtd1295-iso-gpio
22 - realtek,rtd1315e-iso-gpio
23 - realtek,rtd1319-iso-gpio
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/linux-6.12.1/sound/drivers/
Dportman2x4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) by Levent Guendogdu <levon@feature-it.com>
9 * - cleanup and rewrite
11 * - source code cleanup
13 * - fixed compilation problem with alsa 1.0.6a (removed MODULE_CLASSES,
17 * - added 2.6 kernel support
19 …* - added parport_unregister_driver to the startup routine if the driver fails to detect a po…
20 * - added support for all 4 output ports in portman_putmidi
22 * - added checks for opened input device in interrupt handler
24 * - ported from alsa 0.5 to 1.0
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/linux-6.12.1/arch/arm64/boot/dts/st/
Dstm32mp257f-ev1.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
13 #include "stm32mp25-pinctrl.dtsi"
14 #include "stm32mp25xxai-pinctrl.dtsi"
17 model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
18 compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
27 stdout-path = "serial0:115200n8";
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/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32mp157c-odyssey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp157c-odyssey-som.dtsi"
11 model = "Seeed Studio Odyssey-STM32MP157C Board";
12 compatible = "seeed,stm32mp157c-odyssey",
13 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
21 stdout-path = "serial0:115200n8";
26 pinctrl-names = "default", "sleep";
27 pinctrl-0 = <&dcmi_pins_b>;
28 pinctrl-1 = <&dcmi_sleep_pins_b>;
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Dstm32mp15xx-dhcom-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
6 #include "stm32mp15-pinctrl.dtsi"
7 #include "stm32mp15xxaa-pinctrl.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/mfd/st,stpmic1.h>
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
30 compatible = "shared-dma-pool";
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/linux-6.12.1/drivers/scsi/
DNCR5380.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * +1 (303) 666-5836
19 * 1+ (719) 578-3400
20 * 1+ (800) 334-5454
65 * either arbitration is occurring or the phase-indicating signals (
66 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
74 #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
76 #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
79 #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
80 #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
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/linux-6.12.1/drivers/pps/clients/
Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
55 rising_edge = gpiod_get_value(info->gpio_pin); in pps_gpio_irq_handler()
56 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
57 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
58 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
59 else if (info->capture_clear && in pps_gpio_irq_handler()
60 ((rising_edge && info->assert_falling_edge) || in pps_gpio_irq_handler()
61 (!rising_edge && !info->assert_falling_edge))) in pps_gpio_irq_handler()
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/linux-6.12.1/drivers/staging/greybus/
Darche-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2014-2015 Google Inc.
6 * Copyright 2014-2015 Linaro Ltd.
39 WD_STATE_BOOT_INIT, /* WD = falling edge (low) */
40 WD_STATE_COLDBOOT_TRIG, /* WD = rising edge (high), > 30msec */
51 struct gpio_desc *wake_detect; /* bi-dir,maps to WAKE_MOD & WAKE_FRAME signals */
73 /* Requires calling context to hold arche_pdata->platform_state_mutex */
77 arche_pdata->state = state; in arche_platform_set_state()
80 /* Requires arche_pdata->wake_lock is held by calling context */
84 arche_pdata->wake_detect_state = state; in arche_platform_set_wake_detect_state()
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Darche-apb-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2014-2015 Google Inc.
6 * Copyright 2014-2015 Linaro Ltd.
68 struct device *dev = &pdev->dev; in coldboot_seq()
72 if (apb->init_disabled || in coldboot_seq()
73 apb->state == ARCHE_PLATFORM_STATE_ACTIVE) in coldboot_seq()
77 assert_reset(apb->resetn); in coldboot_seq()
79 if (apb->state == ARCHE_PLATFORM_STATE_FW_FLASHING && apb->spi_en) in coldboot_seq()
80 devm_gpiod_put(dev, apb->spi_en); in coldboot_seq()
83 if (!IS_ERR(apb->vcore)) { in coldboot_seq()
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/linux-6.12.1/drivers/usb/dwc3/
Ddwc3-qcom.c1 // SPDX-License-Identifier: GPL-2.0
4 * Inspired by dwc3-of-simple.c
122 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
124 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
127 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
129 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
141 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; in dwc3_qcom_vbus_notifier()
153 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; in dwc3_qcom_host_notifier()
160 struct device *dev = qcom->dev; in dwc3_qcom_register_extcon()
164 if (!of_property_read_bool(dev->of_node, "extcon")) in dwc3_qcom_register_extcon()
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/linux-6.12.1/drivers/pinctrl/starfive/
Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
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Dpinctrl-starfive-jh7110.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
30 #include "../pinctrl-utils.h"
33 #include "pinctrl-starfive-jh7110.h"
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
100 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pin_dbg_show()
102 seq_printf(s, "%s", dev_name(pctldev->dev)); in jh7110_pin_dbg_show()
104 if (pin < sfp->gc.ngpio) { in jh7110_pin_dbg_show()
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); in jh7110_pin_dbg_show()
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); in jh7110_pin_dbg_show()
[all …]
/linux-6.12.1/drivers/ata/
Dpata_octeon_cf.c8 * Copyright (C) 2005 - 2012 Cavium Inc.
31 * -- 8 bits no irq, no DMA
32 * -- 16 bits no irq, no DMA
33 * -- 16 bits True IDE mode with DMA, but no irq.
106 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ in octeon_cf_set_boot_reg_cfg()
108 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ in octeon_cf_set_boot_reg_cfg()
128 struct octeon_cf_port *cf_port = ap->private_data; in octeon_cf_set_piomode()
150 BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T)); in octeon_cf_set_piomode()
154 t2--; in octeon_cf_set_piomode()
158 trh--; in octeon_cf_set_piomode()
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/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-inno-usb2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
50 * enum usb_chg_state - Different states involved in USB charger detection.
89 * struct rockchip_chg_det_reg - usb charger detect registers
92 * @dp_det: assert data pin connect successfully.
115 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
120 * @disfall_en: host disconnect fall edge detection enable.
121 * @disfall_st: host disconnect fall edge detection state.
122 * @disfall_clr: host disconnect fall edge detection clear.
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn10/
Ddcn10_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
33 optc1->tg_regs->reg
36 optc1->base.ctx
40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
45 * apply_front_porch_workaround() - This is a workaround for a bug that has
54 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
55 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
56 timing->v_front_porch = 2; in apply_front_porch_workaround()
58 if (timing->v_front_porch < 1) in apply_front_porch_workaround()
59 timing->v_front_porch = 1; in apply_front_porch_workaround()
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/linux-6.12.1/lib/zstd/decompress/
Dzstd_decompress_block.c5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
14 /*-*******************************************************
50 /*-*************************************************************
63 bpPtr->lastBlock = cBlockHeader & 1; in ZSTD_getcBlockSize()
64 bpPtr->blockType = (blockType_e)((cBlockHeader >> 1) & 3); in ZSTD_getcBlockSize()
65 bpPtr->origSize = cSize; /* only useful for RLE */ in ZSTD_getcBlockSize()
66 if (bpPtr->blockType == bt_rle) return 1; in ZSTD_getcBlockSize()
67 RETURN_ERROR_IF(bpPtr->blockType == bt_reserved, corruption_detected, ""); in ZSTD_getcBlockSize()
79 dctx->litBuffer = (BYTE*)dst + ZSTD_BLOCKSIZE_MAX + WILDCOPY_OVERLENGTH; in ZSTD_allocateLiteralsBuffer()
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/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-pca953x.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <linux/pinctrl/pinconf-generic.h>
135 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
161 * relative. Since first controller (gpio-sch.c) and
162 * second (gpio-dwapb.c) are at the fixed bases, we may
184 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
235 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); in pca953x_bank_shift()
257 * - Standard set, below 0x40, each port can be replicated up to 8 times
258 * - PCA953x standard
263 * - PCA957x with mixed up registers
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/linux-6.12.1/drivers/spi/
Dspi-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
19 #include <linux/dma-mapping.h>
76 #define DRV_NAME "spi-bcm2835"
85 * struct bcm2835_spi - BCM2835 SPI controller
88 * @cs_gpio: chip-select GPIO descriptor
102 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
116 * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
150 * struct bcm2835_spidev - BCM2835 SPI target
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/
Ddc.c90 dc->ctx
93 dc->ctx->logger
95 static const char DC_BUILD_ID[] = "production-build";
100 * DC is the OS-agnostic component of the amdgpu DC driver.
107 * struct dc - The central struct. One per driver. Created on driver load,
110 * struct dc_context - One per driver.
113 * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
116 * struct dc_sink - One per display. Created on boot or hotplug.
119 * sinks (in the Multi-Stream Transport case)
121 * struct resource_pool - One per driver. Represents the hw blocks not in the
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/linux-6.12.1/drivers/tty/serial/
Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
90 /* IER register bits - write only if (EFR[4] == 1) */
103 /* FCR register bits - write only if (EFR[4] == 1) */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
115 * - only on 75x/76x
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/linux-6.12.1/drivers/comedi/drivers/
Dni_mio_common.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for DAQ-STC based boards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
17 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
19 * 340934b.pdf DAQ-STC reference manual
31 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
32 * 321808a.pdf about at-mio-16e-10 rev P
33 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
[all …]
/linux-6.12.1/drivers/net/ethernet/sun/
Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
104 len of non-reassembly pkt
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
185 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
216 reset when hot-swap is being
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/linux-6.12.1/drivers/net/ethernet/intel/e1000/
De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
89 * e1000_set_phy_type - Set the phy type member in the hw struct.
94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
97 switch (hw->phy_id) { in e1000_set_phy_type()
103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
106 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
107 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
108 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
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