Searched full:arranged (Results 1 – 25 of 121) sorted by relevance
12345
17 a bitmap array arranged in 32bit slices where each bit represent signal/line47 HTE lines are arranged in 32 bit slice where each bit represents different
21 struct page arranged in one or more arrays.87 The `mem_section` objects are arranged in a two-dimensional array
17 * The exception fixup information "just so happens" to be arranged
269 * subtracted out. This is arranged so that folks manipulating ISA
19 arranged in vertical stripe.
40 slot for this processor has been loaded. We've arranged
29 The second plane provides 16-bit per-pixel Depth data arranged in
27 are always arranged in memory from left to right, and from top to
19 * Keep this list arranged in rough order of priority. Anything listed after
64 * @node: list pointers, entries arranged in FIFO order
123 * @node: FIFO - arranged in descending order of ack_ackno
34 * arranged as shown below:
154 * arranged as shown below:211 * arranged as shown below:248 * Control-bits are arranged as shown below:278 * They are arranged as shown below:
74 packets of data arranged back to back. It can be done as follows:
122 /* managed XArray arranged in physical block number */258 /* bitlock definitions (arranged in reverse order) */
31 * are arranged for flexibility. We convert the table data to host native
66 * remote node index so the table is arranged in sets of three. The bits are
45 /* The fetch and add registers are allocated here. They are arranged
47 and your userspace is arranged correctly, this will be loaded
97 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
56 Extents are arranged as a tree. Each node of the tree begins with a
75 The number of power domains matches the number of channels, arranged
86 /* Flat array, arranged in groups */
46 /* 16-bit c_can registers can be arranged differently in the memory
12 The driver is arranged by IPs. There are driver components to handle