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/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-370-mirabox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include "armada-370.dtsi"
14 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17 stdout-path = "serial0:115200n8";
30 internal-regs {
35 clock-frequency = <600000000>;
40 compatible = "gpio-leds";
[all …]
Darmada-370-netgear-rn102.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-370.dtsi"
16 compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
19 stdout-path = "serial0:115200n8";
32 internal-regs {
45 nr-ports = <1>;
50 pinctrl-0 = <&ge1_rgmii_pins>;
[all …]
Darmada-370-netgear-rn104.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-370.dtsi"
16 compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";
19 stdout-path = "serial0:115200n8";
32 internal-regs {
44 pinctrl-0 = <&ge0_rgmii_pins>;
45 pinctrl-names = "default";
[all …]
Darmada-370-rd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (RD-88F6710-A1)
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include <dt-bindings/input/input.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
23 #include <dt-bindings/leds/common.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
[all …]
Darmada-370-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6710-BP-DDR3)
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include "armada-370.dtsi"
27 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
30 stdout-path = "serial0:115200n8";
43 internal-regs {
[all …]
Darmada-370-c200-v2.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Device Tree file for Ctera C200-V2
8 /dts-v1/;
10 #include "armada-370.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/leds/common.h>
18 compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp";
22 stdout-path = "serial0:115200n8";
[all …]
Darmada-370-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
20 compatible = "marvell,armada-370-xp";
28 #address-cells = <1>;
29 #size-cells = <0>;
31 compatible = "marvell,sheeva-v7";
38 compatible = "arm,cortex-a9-pmu";
39 interrupts-extended = <&mpic 3>;
43 #address-cells = <2>;
[all …]
Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
[all …]
Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
[all …]
/linux-6.12.1/drivers/mtd/nand/raw/
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
26 * controller when Hamming is chosen:
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
36 * 30B per ECC chunk. Here is the page layout used by the controller
39 * +-----------------------------------------
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/linux-6.12.1/drivers/bus/
Dmvebu-mbus.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * - One to configure the access of the CPU to the devices. Depending
17 * - One to configure the access to the CPU to the SDRAM. There are
23 * - Reads out the SDRAM address decoding windows at initialization
30 * devices have to configure those device -> SDRAM windows to ensure
33 * - Provides an API for platform code or device drivers to
34 * dynamically add or remove address decoding windows for the CPU ->
39 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
40 * see the list of CPU -> SDRAM windows and their configuration
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