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230 … reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the …235 … reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the …240 …s L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the …245 …s L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the …250 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …255 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…260 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …265 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…270 … reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the …275 … reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the …[all …]
280 … the LSU is processing an L1-hit, OR when the NTF instruction merged with another load in the LMQ",491 …ion": "Percentage of demand loads that reloaded using modified data from another core's L2 or L3 o…498 …ption": "Percentage of demand loads that reloaded using shared data from another core's L2 or L3 o…526 …ion": "Percentage of demand loads that reloaded using modified data from another core's L2 or L3 o…533 …ption": "Percentage of demand loads that reloaded using shared data from another core's L2 or L3 o…824 …"BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the …831 …"BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the …838 …"BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the …845 …"BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the …852 …"BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on the …[all …]
15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …35 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…60 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…75 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on t…80 …The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the …95 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…135 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or…150 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a…[all …]
30 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on t…35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…80 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the …90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…95 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the …100 …eing held at dispatch because it lost arbitration onto the issue pipe to another instruction (from…145 … from beyond the local L3. The source could be local/remote/distant memory or another core's cache"160 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a…190 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…235 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…[all …]
10 … the core's L3 data cache. The source could be local/remote/distant memory or another core's cache"20 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the …25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…70 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on …95 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on …100 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on …120 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …180 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…185 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the …190 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…[all …]
25 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group…40 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on t…50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the …55 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…80 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …100 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…
5 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the …50 …n": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on …115 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the …155 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L…170 …"BriefDescription": "Duration in cycles to reload either shared or modified data from another core…195 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …280 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 o…315 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on …330 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…335 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…[all …]
35 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…41 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or…47 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…53 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L…59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…65 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Gr…71 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…77 …"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or G…251 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a…257 …"BriefDescription": "Duration in cycles to reload either shared or modified data from another core…[all …]
89 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…90 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…95 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…96 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…203 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a…204 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a…[all …]
371 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…372 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…377 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…378 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…383 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…384 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…389 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…390 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…401 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …402 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …[all …]
5 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…6 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…107 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a…108 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a…113 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on t…114 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on t…[all …]
29 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 o…35 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…107 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a…113 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on t…119 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 o…125 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…131 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…35 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…36 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same N…41 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…42 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…95 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…101 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …107 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …
21 …e blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."28 …y the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."49 …U and are blocked because the SHA coprocessor is busy performing a function issued by another CPU."56 …issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU."77 …d are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."84 …ed by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."105 …d are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."112 …ed by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."133 …U and are blocked because the ECC coprocessor is busy performing a function issued by another CPU."140 …issued by the CPU because the ECC coprocessor is busy performing a function issued by another CPU."
21 …e blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."28 …y the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."49 …U and are blocked because the SHA coprocessor is busy performing a function issued by another CPU."56 …issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU."77 …d are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."84 …ed by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."105 …d are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."112 …ed by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
436 …"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from t…447 …"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to thi…656 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…668 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…680 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…692 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…704 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…716 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…728 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…740 …"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different…[all …]
79 when one growing tree reaches the root of another? That can happen in82 the root of another"; there's also open-by-fhandle stuff, and there's a84 to another and we run into it when we do a lookup.105 root of one tree becoming a child of directory in another. In particular,118 another filesystem; it may be ecryptfs doing operation in the underlying186 one directory and blocked on attempt to lock another. That leaves221 of another - otherwise the operation would not have progressed past228 It can't be a parent and a child of another parent either.230 of another child.234 neither of the children is a descendent of another.[all …]
102 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…114 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…156 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the sa…168 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in a diff…174 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the sa…192 …"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the …348 …"BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA…360 …"BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different N…396 …"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address…408 …"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address…
188 /* Restart another partition */196 /* Boot another partition */200 /* Stop this or another partition */204 /* Copy data from one partition to another */212 /* Get a property from another guest's device tree */216 /* Set a property in another guest's device tree */