accesses (full) in projects: linux-6.12.1

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/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
D	l2_cache.json	4 …accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are for mis… 8 …e for data and instruction accesses. Accesses are for misses in the level 1 caches or translation … 20 …accesses due to memory read operations. level 2 cache is a unified cache for data and instruction … 24 …accesses due to memory write operations. level 2 cache is a unified cache for data and instruction… 28 …accesses due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache fo… 32 …accesses due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache f…
D	metrics.json	47 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 82 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 89 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 103 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 117 … the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction… 124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed … 131 …res the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instructio… 138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… [all …]
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 36 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 40 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even… 48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This… 60 …"PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data … 64 …"PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data…
D	memory.json	`4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 12 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 16 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 20 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m…`
D	l3_cache.json	`8 "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." 12 …accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for mis…`
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
D	l2_cache.json	4 …accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are for mis… 8 …e for data and instruction accesses. Accesses are for misses in the level 1 caches or translation … 20 …accesses due to memory read operations. level 2 cache is a unified cache for data and instruction … 24 …accesses due to memory write operations. level 2 cache is a unified cache for data and instruction… 28 …accesses due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache fo… 32 …accesses due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache f…
D	metrics.json	54 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 93 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 100 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 114 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 128 … the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction… 135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed … 142 …res the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instructio… 149 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… [all …]
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 36 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 40 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even… 48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This… 60 …"PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data … 64 …"PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data…
D	memory.json	`4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 12 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 16 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 20 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m…`
D	l3_cache.json	`8 "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." 12 …accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for mis…`
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
D	l2_cache.json	4 …accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are for mis… 8 …e for data and instruction accesses. Accesses are for misses in the level 1 caches or translation … 20 …accesses due to memory read operations. level 2 cache is a unified cache for data and instruction … 24 …accesses due to memory write operations. level 2 cache is a unified cache for data and instruction… 28 …accesses due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache fo… 32 …accesses due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache f…
D	metrics.json	55 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 94 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 101 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 108 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 115 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 122 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 129 … the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction… 136 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed … 143 …res the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instructio… 150 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… [all …]
D	memory.json	4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 12 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 16 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 20 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m… 24 …"PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred… 28 …"PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additiona… 36 …"PublicDescription": "Counts the number of memory read and write accesses in a cycle that are tag … 40 …"PublicDescription": "Counts the number of memory read accesses in a cycle that are tag checked by… 44 …"PublicDescription": "Counts the number of memory write accesses in a cycle that is tag checked by…
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 36 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 40 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even… 48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This… 60 …"PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data … 64 …"PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data…
D	l3_cache.json	`8 "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." 12 …accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for mis…`
/linux-6.12.1/tools/perf/Documentation/
D	perf-c2c.txt	37 for cachelines with highest contention - highest number of HITM accesses. 196 - cacheline percentage of all Remote/Local HITM accesses 199 - cacheline percentage of all peer accesses 208 - sum of all cachelines accesses 211 - sum of all load accesses 214 - sum of all store accesses 217 L1Hit - store accesses that hit L1 218 L1Miss - store accesses that missed L1 219 N/A - store accesses with memory level is not available 225 - count of LLC load accesses, includes LLC hits and LLC HITMs [all …]
/linux-6.12.1/tools/memory-model/Documentation/
D	ordering.txt	15 2. Ordered memory accesses. These operations order themselves 16 against some or all of the CPU's prior accesses or some or all 17 of the CPU's subsequent accesses, depending on the subcategory 20 3. Unordered accesses, as the name indicates, have no ordering 48 a device driver, which must correctly order accesses to a physical 68 accesses against all subsequent accesses from the viewpoint of all CPUs. 89 CPU's accesses into three groups: 242 Ordered Memory Accesses 245 The Linux kernel provides a wide variety of ordered memory accesses: 264 of the CPU's prior memory accesses. Release operations often provide [all …]
D	access-marking.txt	1 MARKING SHARED-MEMORY ACCESSES 5 normal accesses to shared memory, that is "normal" as in accesses that do 7 document these accesses, both with comments and with special assertions 18 1. Plain C-language accesses (unmarked), for example, "a = b;" 39 Neither plain C-language accesses nor data_race() (#1 and #2 above) place 46 C-language accesses. It is permissible to combine #2 and #3, for example, 51 C-language accesses, but marking all accesses involved in a given data 60 data_race() and even plain C-language accesses is preferable to 88 reads can enable better checking of the remaining accesses implementing 135 the other accesses to the relevant shared variables. But please note [all …]
/linux-6.12.1/Documentation/dev-tools/
D	kcsan.rst	78 the racing thread, but could also occur due to e.g. DMA accesses. Such reports 85 It may be desirable to disable data race detection for specific accesses, 90 any data races due to accesses in ``expr`` should be ignored and resulting 92 `"Marking Shared-Memory Accesses" in the LKMM`_ for more information. 95 to document that all data races due to accesses to a variable are intended 124 .. _"Marking Shared-Memory Accesses" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/t… 138 accesses are aligned writes up to word size. 200 In an execution, two memory accesses form a data race if they conflict, 204 Accesses and Data Races" in the LKMM`_. 206 .. _"Plain Accesses and Data Races" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/to… [all …]
/linux-6.12.1/include/linux/
D	kcsan-checks.h	4 * uninstrumented accesses, or change KCSAN checking behaviour of accesses. 87 * Accesses within the atomic region may appear to race with other accesses but 100 * Accesses within the atomic region may appear to race with other accesses but 111 * kcsan_atomic_next - consider following accesses as atomic 113 * Force treating the next n memory accesses for the current context as atomic 116 * @n: number of following memory accesses to treat as atomic. 123 * Set the access mask for all accesses for the current context if non-zero. 163 * Scoped accesses are implemented by appending @sa to an internal list for the 223 * Only use these to disable KCSAN for accesses in the current compilation unit; 323 * Check for atomic accesses: if atomic accesses are not ignored, this simply [all …]
/linux-6.12.1/Documentation/core-api/
D	unaligned-memory-access.rst	2 Unaligned Memory Accesses 15 unaligned accesses, why you need to write code that doesn't cause them, 22 Unaligned memory accesses occur when you try to read N bytes of data starting 59 - Some architectures are able to perform unaligned memory accesses 61 - Some architectures raise processor exceptions when unaligned accesses 64 - Some architectures raise processor exceptions when unaligned accesses 72 memory accesses to happen, your code will not work correctly on certain 103 to pad structures so that accesses to fields are suitably aligned (assuming 136 lead to unaligned accesses when accessing fields that do not satisfy 183 Here is another example of some code that could cause unaligned accesses:: [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/elkhartlake/
D	frontend.json	`55 "EventName": "ICACHE.ACCESSES", 56 … accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count … 65 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count… 74 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count…`
/linux-6.12.1/tools/perf/pmu-events/arch/x86/snowridgex/
D	frontend.json	`55 "EventName": "ICACHE.ACCESSES", 56 … accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count … 65 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count… 74 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count…`
/linux-6.12.1/kernel/kcsan/
D	permissive.h	3 * Special rules for ignoring entire classes of data-racy memory accesses. None 44 * Rules here are only for plain read accesses, so that we still report in kcsan_ignore_data_race() 45 * data races between plain read-write accesses. in kcsan_ignore_data_race() 60 * While it is still recommended that such accesses be marked in kcsan_ignore_data_race() 66 * optimizations (including those that tear accesses), because no more in kcsan_ignore_data_race() 67 * than 1 bit changed, the plain accesses are safe despite the presence in kcsan_ignore_data_race()
/linux-6.12.1/tools/testing/selftests/bpf/progs/
D	user_ringbuf_fail.c	40 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should 63 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should 83 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should 103 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should 125 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should 145 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should 165 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should 183 /* A callback that accesses a dynptr in a bpf_user_ringbuf_drain callback should

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