| /linux-6.12.1/arch/arm/boot/dts/amlogic/ |
| D | meson6.dtsi | 51 clocks = <&xtal>, <&clk81>;
52 clock-names = "xtal", "pclk";
56 clocks = <&xtal>, <&clk81>, <&clk81>;
57 clock-names = "xtal", "pclk", "baud";
61 clocks = <&xtal>, <&clk81>, <&clk81>;
62 clock-names = "xtal", "pclk", "baud";
66 clocks = <&xtal>, <&clk81>, <&clk81>;
67 clock-names = "xtal", "pclk", "baud";
71 clocks = <&xtal>, <&clk81>, <&clk81>;
72 clock-names = "xtal", "pclk", "baud";
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| D | meson8.dtsi | 256 clocks = <&xtal>;
257 clock-names = "xtal";
581 xtal_32k_out_pins: xtal-32k-out {
584 function = "xtal";
630 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
631 clock-names = "xtal", "ddr_pll";
718 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
727 clocks = <&xtal>,
753 clocks = <&xtal>, <&clkc CLKID_CLK81>;
754 clock-names = "xtal", "pclk";
[all …]
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| D | meson8b.dtsi | 233 clocks = <&xtal>;
234 clock-names = "xtal";
591 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
592 clock-names = "xtal", "ddr_pll";
693 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
702 clocks = <&xtal>,
724 clocks = <&xtal>, <&clkc CLKID_CLK81>;
725 clock-names = "xtal", "pclk";
730 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
731 clock-names = "xtal", "pclk", "baud";
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | armada3700-xtal-clock.txt | 1 * Xtal Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
12 "marvell,armada-3700-xtal-clock"
17 output names ("xtal")
24 xtalclk: xtal-clk {
25 compatible = "marvell,armada-3700-xtal-clock";
26 clock-output-names = "xtal";
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| D | marvell,armada-3700-uart-clock.yaml | 23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
28 used for UART (most probably xtal) for smooth boot log on UART.
36 - const: xtal
57 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
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| D | silabs,si5351.yaml | 50 - const: xtal
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
106 2 - use XTAL for this output
212 /* Connect XTAL input to 25MHz reference */
214 clock-names = "xtal";
216 /* Use XTAL input as source of PLL0 and PLL1 */
258 * - XTAL as clock source of output divider
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| D | amlogic,s4-pll-clkc.yaml | 25 - const: xtal
44 clocks = <&xtal>;
45 clock-names = "xtal";
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| D | amlogic,meson8-ddr-clkc.yaml | 26 - const: xtal
45 clocks = <&xtal>;
46 clock-names = "xtal";
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| /linux-6.12.1/arch/arm64/boot/dts/amlogic/ |
| D | amlogic-t7-a311d2-an400.dts | 27 xtal: xtal-clk { label
30 clock-output-names = "xtal";
36 clocks = <&xtal>, <&xtal>, <&xtal>;
37 clock-names = "xtal", "pclk", "baud";
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| D | amlogic-t7-a311d2-khadas-vim4.dts | 41 xtal: xtal-clk { label
44 clock-output-names = "xtal";
52 clocks = <&xtal>, <&xtal>, <&xtal>;
53 clock-names = "xtal", "pclk", "baud";
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| D | amlogic-a4-common.dtsi | 23 xtal: xtal-clk { label
26 clock-output-names = "xtal";
58 clocks = <&xtal>;
66 clocks = <&xtal>, <&xtal>, <&xtal>;
67 clock-names = "xtal", "pclk", "baud";
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| D | meson-gxbb.dtsi | 286 clocks = <&xtal>, <&clkc CLKID_CLK81>;
287 clock-names = "xtal", "mpeg-clk";
322 assigned-clock-parents = <&xtal>, <0>;
330 clocks = <&xtal>;
331 clock-names = "xtal";
789 clocks = <&xtal>,
838 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
839 clock-names = "xtal", "pclk", "baud";
843 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
844 clock-names = "xtal", "pclk", "baud";
[all …]
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| D | meson-gxl.dtsi | 310 clocks = <&xtal>, <&clkc CLKID_CLK81>;
311 clock-names = "xtal", "mpeg-clk";
334 assigned-clock-parents = <&xtal>, <0>;
342 clocks = <&xtal>;
343 clock-names = "xtal";
859 clocks = <&xtal>,
908 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
909 clock-names = "xtal", "pclk", "baud";
913 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
914 clock-names = "xtal", "pclk", "baud";
[all …]
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| D | meson-a1.dtsi | 306 <&xtal>;
309 "hifi_pll", "xtal";
328 clocks = <&xtal>, <&xtal>, <&xtal>;
329 clock-names = "xtal", "pclk", "baud";
338 clocks = <&xtal>, <&xtal>, <&xtal>;
339 clock-names = "xtal", "pclk", "baud";
350 clocks = <&xtal>,
395 clock-names = "xtal";
446 assigned-clock-parents = <&xtal>;
526 xtal: xtal-clk { label
[all …]
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| D | meson-s4.dtsi | 62 xtal: xtal-clk { label
65 clock-output-names = "xtal";
121 <&xtal>;
125 "mpll2", "mpll3", "hdmi_pll", "xtal";
132 clocks = <&xtal>;
133 clock-names = "xtal";
140 clocks = <&xtal>;
606 <&xtal>,
755 clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>;
756 clock-names = "xtal", "pclk", "baud";
[all …]
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| /linux-6.12.1/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 70 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
105 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
106 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
107 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
109 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
110 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
112 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
113 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
114 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
117 PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
[all …]
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| /linux-6.12.1/drivers/media/dvb-frontends/ |
| D | cxd2841er.c | 60 enum cxd2841er_xtal xtal; member
312 static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz) in cxd2841er_calc_iffreq_xtal() argument
317 do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000)); in cxd2841er_calc_iffreq_xtal()
792 switch (priv->xtal) { in cxd2841er_shutdown_to_sleep_s()
805 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n", in cxd2841er_shutdown_to_sleep_s()
806 __func__, priv->xtal); in cxd2841er_shutdown_to_sleep_s()
854 switch (priv->xtal) { in cxd2841er_shutdown_to_sleep_tc()
2122 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C; in cxd2841er_dvbt2_set_profile()
2127 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28; in cxd2841er_dvbt2_set_profile()
2132 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28; in cxd2841er_dvbt2_set_profile()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/serial/ |
| D | amlogic,meson-uart.yaml | 70 - description: external xtal clock identifier
72 - description: the source of the baudrate generator, can be either the xtal or the pclk
76 - const: xtal
100 clocks = <&xtal>, <&pclk>, <&xtal>;
101 clock-names = "xtal", "pclk", "baud";
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| /linux-6.12.1/drivers/media/pci/cx18/ |
| D | cx18-av-audio.c | 66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
101 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
105 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ in set_audclk_freq()
109 /* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */ in set_audclk_freq()
136 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
140 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/ in set_audclk_freq()
144 /* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */ in set_audclk_freq()
173 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
[all …]
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| /linux-6.12.1/drivers/clk/ralink/ |
| D | clk-mtmips.c | 172 { CLK_PERIPH("480000.wmac", "xtal") }
185 { CLK_PERIPH("10180000.wmac", "xtal") }
198 { CLK_PERIPH("10180000.wmac", "xtal") }
210 { CLK_PERIPH("10180000.wmac", "xtal") }
223 { CLK_PERIPH("10300000.wmac", "xtal") }
267 CLK_FIXED("xtal", NULL, 40000000)
271 CLK_FIXED("periph", "xtal", 40000000)
275 CLK_FIXED("pcmi2s", "xtal", 480000000),
276 CLK_FIXED("periph", "xtal", 40000000)
680 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/amlogic/ |
| D | amlogic,meson-gx-hhi-sysctrl.yaml | 111 clocks = <&xtal>;
112 clock-names = "xtal";
156 clocks = <&xtal>, <&clk81>;
157 clock-names = "xtal", "mpeg-clk";
170 clocks = <&xtal>;
171 clock-names = "xtal";
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| /linux-6.12.1/drivers/clk/mvebu/ |
| D | armada-37xx-xtal.c | 3 * Marvell Armada 37xx SoC xtal clocks
22 const char *xtal_name = "xtal"; in armada_3700_xtal_clock_probe()
74 { .compatible = "marvell,armada-3700-xtal-clock", },
82 .name = "marvell-armada-3700-xtal-clock",
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| /linux-6.12.1/drivers/clk/renesas/ |
| D | rcar-usb2-clock-sel.c | 40 bool xtal; member
49 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only()
51 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only()
57 if (priv->extal && !priv->xtal) in usb2_clock_sel_disable_extal_only()
169 priv->xtal = !!clk_get_rate(clk); in rcar_usb2_clock_sel_probe()
173 if (!priv->extal && !priv->xtal) { in rcar_usb2_clock_sel_probe()
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| /linux-6.12.1/drivers/phy/ralink/ |
| D | phy-mt7621-pci.c | 70 * @sys_clk: pointer to the system XTAL clock
127 /* Debug Xtal Type */ in mt7621_set_phy_for_ssc()
142 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
147 dev_dbg(dev, "Xtal is 40MHz\n"); in mt7621_set_phy_for_ssc()
174 dev_dbg(dev, "Xtal is 25MHz\n"); in mt7621_set_phy_for_ssc()
175 } else { /* 20MHz Xtal */ in mt7621_set_phy_for_ssc()
179 dev_dbg(dev, "Xtal is 20MHz\n"); in mt7621_set_phy_for_ssc()
199 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ieee802154/ |
| D | at86rf230.txt | 15 - xtal-trim: u8 value for fine tuning the internal capacitance
16 arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF
26 xtal-trim = /bits/ 8 <0x06>;
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