Searched full:vdw (Results 1 – 4 of 4) sorted by relevance
| /linux-6.12.1/drivers/clk/versatile/ |
| D | clk-icst.h | 9 ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */
10 ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */
12 ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */
13 ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */
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| D | clk-icst.c | 164 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
174 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
184 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
192 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
439 /* Minimum 12 MHz, VDW = 4 */
442 * Maximum 160 MHz, VDW = 152 for all core modules, but
444 * go to 200 MHz (max VDW = 192).
457 /* Minimum 3 MHz, VDW = 4 */
459 /* Maximum 50 MHz, VDW = 192 */
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | arm,syscon-icst.yaml | 25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
35 Hardware variant RDW OD VDW
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| /linux-6.12.1/drivers/gpu/drm/v3d/ |
| D | v3d_perfmon.c | 39 …{"VPM", "VPM-total-clk-cycles-VDW-stalled", "[VPM] Total clock cycles VDW is stalled waiting for V…
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