Searched full:uarts (Results 1 – 25 of 121) sorted by relevance
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| /linux-6.12.1/Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
94 CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断发送到AVECINTC，而后通过AVECINTC直接
104 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/aspeed/ |
| D | uart-routing.yaml | 17 the built-in UARTS and physical serial I/O ports.
20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to
24 which owns the system configuration policy, to configure how UARTs and
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| /linux-6.12.1/Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
33 | LIOINTC | <-- | UARTs |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
70 | EIOINTC | | LIOINTC | <-- | UARTs |
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
102 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
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| /linux-6.12.1/Documentation/translations/zh_TW/arch/loongarch/ |
| D | irq-chip-model.rst | 27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
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| /linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/include/ |
| D | chipcommon.h | 156 /* UARTs */
233 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
235 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
236 /* UARTs are driven by internal divided clock */
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
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| /linux-6.12.1/drivers/tty/serial/8250/ |
| D | Kconfig | 182 This enables support for FPGA based UARTs found on many MEN
184 and 16z125 UARTs.
388 erratum for Freescale 16550 UARTs in the 8250 driver. It also
396 driver for the Altera 16550 UART. One or more Altera 16550 UARTs
501 its UARTs, say Y to this option. If unsure, say N.
539 I/O UARTs that are not covered by the more generic SERIAL_8250_PCI
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| D | 8250_pxa.c | 3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
169 MODULE_DESCRIPTION("driver for PXA on-board UARTS");
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| /linux-6.12.1/drivers/tty/serial/ |
| D | Kconfig | 136 This enables the driver for the on-chip UARTs of the Atmel
169 Say Y here if you wish to have the internal AT91 UARTs
172 64). This is necessary if you also want other UARTs, such as
173 external 8250/16C550 compatible UARTs.
206 This enables the driver for the on-chip UARTs of the Amlogic
226 This enables the driver for the on-chip UARTs of the Cirrus
244 Support for the on-chip UARTs on the Samsung
280 Support for the on-chip UARTs on the NVIDIA Tegra series SOCs
681 Those are UARTs completely different from the Standard UARTs on the
755 UARTs.
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| /linux-6.12.1/arch/parisc/include/asm/ |
| D | serial.h | 6 * This is used for 16550-compatible UARTs
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| /linux-6.12.1/include/uapi/linux/ |
| D | serial_core.h | 27 #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */
143 /* Altera UARTs */
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| D | serial_reg.h | 98 some Freescale UARTs) */
239 * The Intel XScale on-chip UARTs define these bits
348 * Extra serial register definitions for the internal UARTs
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm7120-l2-intc.yaml | 24 controller, in particular for UARTs
116 typically UARTs. Setting these bits will make their respective interrupt
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| /linux-6.12.1/drivers/char/mwave/ |
| D | Makefile | 12 # To have the mwave driver disable other uarts if necessary
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| /linux-6.12.1/arch/mips/include/asm/mach-rc32434/ |
| D | irq.h | 17 /* 16550 UARTs */
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| /linux-6.12.1/include/linux/ssb/ |
| D | ssb_driver_extif.h | 11 * support external devices such as UARTs and the BCM2019 Bluetooth
13 * The external interface core also contains 2 on-chip 16550 UARTs, clock
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| D | ssb_driver_chipcommon.h | 8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
29 #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
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| /linux-6.12.1/arch/x86/kernel/ |
| D | jailhouse.c | 183 * platform UARTs since setup data version 2. in jailhouse_serial_workaround()
185 * In case of version 1, we don't know which UARTs belong Linux. In in jailhouse_serial_workaround()
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| /linux-6.12.1/arch/arm/mach-s3c/ |
| D | dev-uart-s3c64xx.c | 25 /* 64xx uarts are closer together */
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| D | pm-common.c | 43 * restore the UARTs state yet
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| /linux-6.12.1/drivers/platform/x86/ |
| D | serdev_helpers.h | 12 * create a serdev-controller device for these UARTs instead of a /dev/ttyS#.
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| /linux-6.12.1/Documentation/devicetree/bindings/serial/ |
| D | 8250_omap.yaml | 7 title: 8250 compliant UARTs on TI's OMAP2+ and K3 SoCs
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| D | qcom,msm-uartdm.yaml | 20 Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
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| /linux-6.12.1/drivers/tty/serial/jsm/ |
| D | jsm_driver.c | 131 * 2 I/O Mapped UARTs and Status in jsm_probe_one()
133 * 4 Memory Mapped UARTs and Status in jsm_probe_one()
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| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | starfive,jh7110-sys-pinctrl.yaml | 16 includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
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| /linux-6.12.1/Documentation/driver-api/serial/ |
| D | serial-iso7816.rst | 14 Some CPUs/UARTs (e.g., Microchip AT91) contain a built-in mode capable of
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