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Searched full:tegra210_clk_pll_p (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-vi.yaml205 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
206 <&tegra_car TEGRA210_CLK_PLL_P>,
207 <&tegra_car TEGRA210_CLK_PLL_P>;
Dnvidia,tegra20-host1x.yaml424 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
425 <&tegra_car TEGRA210_CLK_PLL_P>,
426 <&tegra_car TEGRA210_CLK_PLL_P>;
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra210.c2453 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2571 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
3548 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3549 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3550 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3551 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3559 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3560 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3562 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3563 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
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/linux-6.12.1/include/dt-bindings/clock/
Dtegra210-car.h274 #define TEGRA210_CLK_PLL_P 243 macro
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164 <&tegra_car TEGRA210_CLK_PLL_P>,
165 <&tegra_car TEGRA210_CLK_PLL_P>;
1387 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;