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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Ddavinci-mcbsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcbsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bastien Curutchet <bastien.curutchet@bootlin.com>
13 - $ref: dai-common.yaml#
18 - ti,da850-mcbsp
23 - description: CFG registers
24 - description: data registers
26 reg-names:
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/linux-6.12.1/drivers/net/wan/
Dfarsync.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
23 * used with the FarSite T-Series cards (T2P & T4P) running in the high
30 * purpose (FarSite T-series).
116 unsigned char framing; /* E1, T1 or J1 */ member
121 unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
126 unsigned char rxBufferMode; /* rx elastic buffer depth */
129 unsigned int receiveBufferDelay; /* delay thro rx buffer timeslots */
130 unsigned int framingErrorCount; /* framing errors */
193 #define T1 5 macro
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Dfarsync.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
71 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
94 * file. Unfortunately various name clashes and the non-portability of the
163 #define cnv_bcnt(len) (-(len))
169 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
170 #define RX_FRAM 0x20 /* Rx: framing error */
171 #define RX_OFLO 0x10 /* Rx: overflow error */
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Dixp4xx_hss.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
13 #include <linux/dma-mapping.h>
47 #define RX_DESCS 16 /* also length of all RX queues */
90 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
119 /* TX/RX endianness, default = LSB */
125 /* No framing bit transmitted and expected on RX? (default = framing bit) */
139 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
142 /* 56k data endiannes - which bit unused: high (default) or low */
180 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
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/linux-6.12.1/sound/soc/ti/
Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
30 #include "edma-pcm.h"
31 #include "davinci-i2s.h"
33 #define DRV_NAME "davinci-i2s"
38 * - This driver supports the "Audio Serial Port" (ASP),
41 * - But it labels it a "Multi-channel Buffered Serial Port"
43 * backward-compatible, possibly explaining that confusion.
45 * - OMAP chips have a controller called McBSP, which is
48 * - Newer DaVinci chips have a controller called McASP,
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/linux-6.12.1/drivers/net/ethernet/sun/
Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
78 #define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing
81 from RX FIFO to host mem.
82 RX completion reg updated.
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/linux-6.12.1/drivers/media/i2c/
Dov5640.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright (C) 2014-2017 Mentor Graphics Inc.
8 #include <linux/clk-provider.h>
22 #include <media/v4l2-async.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-subdev.h>
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