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/linux-6.12.1/Documentation/devicetree/bindings/usb/
Dnvidia,tegra210-xusb.yaml42 - description: XUSB SuperSpeed clock
43 - description: XUSB SuperSpeed clock divider
44 - description: XUSB SuperSpeed source clock
68 - description: reset for the SuperSpeed logic
104 - description: XUSBA power domain (for SuperSpeed)
Dnvidia,tegra124-xusb.yaml50 - description: XUSB SuperSpeed clock
51 - description: XUSB SuperSpeed clock divider
52 - description: XUSB SuperSpeed source clock
76 - description: reset for the SuperSpeed logic
Dmicrochip,usb5744.yaml10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
14 speeds. The new SuperSpeed hubs operate in parallel with the USB 2.0
15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
Dsnps,dwc3.yaml237 When set, all SuperSpeed bus instances in park mode are disabled.
321 flow-controlled endpoint. It is only used for SuperSpeed.
322 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
338 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
350 for SuperSpeed operation.
351 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
364 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
Dnvidia,tegra234-xusb.yaml43 - description: XUSB SuperSpeed clock
44 - description: XUSB SuperSpeed source clock
102 - description: XUSBA power domain (for SuperSpeed)
Dnvidia,tegra194-xusb.yaml39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
98 - description: XUSBA power domain (for SuperSpeed)
Dnvidia,tegra186-xusb.yaml39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
97 - description: XUSBA power domain (for SuperSpeed)
Dnvidia,tegra-xudc.yaml11 USB 3.0 SuperSpeed protocols.
79 - description: XUSBA(superspeed) power-domain
Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
Dfsl,ls1028a.yaml7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
Dusb-switch.yaml25 description: Possible handler of SuperSpeed signals retiming
Dti,hd3ss3220.yaml13 HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sc8280xp.yaml32 - description: Primary USB SuperSpeed pipe clock
40 - description: Secondary USB SuperSpeed pipe clock
48 - description: Multiport USB first SuperSpeed pipe clock
49 - description: Multiport USB second SuperSpeed pipe clock
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dqcom,usb-ss.yaml7 title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
13 Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
30 - description: SuperSpeed pipe clock
/linux-6.12.1/drivers/usb/dwc3/
Ddwc3-octeon.c30 /* Reference clock select for SuperSpeed and HighSpeed PLLs:
33 * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
35 * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
60 /* Enable reference clock to prescaler for SuperSpeed functionality.
101 /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
105 /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
326 /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ in dwc3_octeon_setup()
329 /* Step 5c: Enable SuperSpeed. */ in dwc3_octeon_setup()
/linux-6.12.1/Documentation/driver-api/usb/
Dusb3-debug-port.rst75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
143 [ 79.454780] usb 2-2.1: new SuperSpeed USB device number 3 using xhci_hcd
Dpower-management.rst655 another hub. The expectation is that all superspeed ports have a
662 peer ports are simply the hi-speed and superspeed interface pins that
666 While a superspeed port is powered off a device may downgrade its
671 before their superspeed peer is permitted to power-off. The implication is
672 that the setting ``pm_qos_no_power_off`` to zero on a superspeed port may
675 if it wants to guarantee that a superspeed port will power-off.
677 2. Port resume is sequenced to force a superspeed port to power-on prior to its
Ddwc3.rst2 Synopsys DesignWare Core SuperSpeed USB 3.0 Controller
11 The *Synopsys DesignWare Core SuperSpeed USB 3.0 Controller*
12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant
41 your IP team and/or *Synopsys DesignWare Core SuperSpeed USB 3.0
53 7. SuperSpeed Bulk Streams
89 to a value that's divisible by *wMaxPacketSize* (1024 on SuperSpeed,
/linux-6.12.1/drivers/usb/core/
Dport.c520 * may miss a suspend event for the SuperSpeed port. in link_peers()
537 * The SuperSpeed reference is dropped when the HiSpeed port in in link_peers()
539 * SuperSpeed connection to drop since there is no risk of a in link_peers()
575 * usb_port_runtime_resume() event which takes a SuperSpeed ref in unlink_peers()
593 /* Drop the SuperSpeed ref held on behalf of the active HiSpeed port */ in unlink_peers()
/linux-6.12.1/include/linux/usb/
Dgadget.h219 * @comp_desc: In case of SuperSpeed support, this is the endpoint companion
349 * @ssp_rate: Current connected SuperSpeed Plus signaling rate and lane count.
350 * @max_ssp_rate: Maximum SuperSpeed Plus signaling rate and lane count the UDC
424 /* USB SuperSpeed Plus only */
573 * gadget_is_superspeed() - return true if the hardware handles superspeed
574 * @g: controller that might support superspeed
583 * superspeed plus
584 * @g: controller that might support superspeed plus
Dch9.h35 /* USB 3.2 SuperSpeed Plus phy signaling rate generation and lane count */
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-a311d-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
Dmeson-g12b-s922x-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
/linux-6.12.1/drivers/usb/mtu3/
DKconfig13 Dual Role SuperSpeed USB controller. You can select usb
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8-apalis-eval.dtsi122 /* TODO: Apalis USBH4 SuperSpeed */

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