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/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
30 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
31 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
32 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
33 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
34 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
35 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
36 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
37 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */
[all …]
Dsparx5_vcap_impl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * https://github.com/microchip-ung/sparx-5_reginfo
24 #define SPARX5_VCAP_CID_IS0_L5 VCAP_CID_INGRESS_L5 /* IS0/CLM lookup 5 */
26 (VCAP_CID_INGRESS_L5 + VCAP_CID_LOOKUP_SIZE - 1) /* IS0/CLM Max */
33 (VCAP_CID_INGRESS_STAGE2_L3 + VCAP_CID_LOOKUP_SIZE - 1) /* IS2 Max */
36 #define SPARX5_VCAP_CID_ES0_MAX (VCAP_CID_EGRESS_L1 - 1) /* ES0 Max */
41 (VCAP_CID_EGRESS_STAGE2_L1 + VCAP_CID_LOOKUP_SIZE - 1) /* ES2 Max */
94 /* IS2 non-ethernet traffic type keyset generation */
Dsparx5_fdma.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/dma-mapping.h>
30 *dataptr = fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + in sparx5_fdma_tx_dataptr_cb()
31 ((dcb * fdma->n_dbs + db) * fdma->db_size); in sparx5_fdma_tx_dataptr_cb()
39 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb()
40 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb()
43 skb = __netdev_alloc_skb(rx->ndev, fdma->db_size, GFP_ATOMIC); in sparx5_fdma_rx_dataptr_cb()
45 return -ENOMEM; in sparx5_fdma_rx_dataptr_cb()
47 *dataptr = virt_to_phys(skb->data); in sparx5_fdma_rx_dataptr_cb()
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Dsparx5_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
32 * (1/1000000)/((2^-59)/X) in sparx5_ptp_get_1ppm()
37 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
59 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
81 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set()
89 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_ptp_hwtstamp_set()
90 return -EINVAL; in sparx5_ptp_hwtstamp_set()
92 switch (cfg->tx_type) { in sparx5_ptp_hwtstamp_set()
94 port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; in sparx5_ptp_hwtstamp_set()
[all …]
Dsparx5_main.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
137 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */
138 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */
139 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */
155 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */
156 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */
182 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */
183 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */
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Dsparx5_tc_flower.c1 // SPDX-License-Identifier: GPL-2.0+
39 /* SparX-5 VCAP fragment types:
41 * 2 = suspicious fragment, 3 = valid follow-up fragment
57 /* 0/0 0/1 1/0 1/1 <-- first_frag */
65 switch (st->tpid) { in sparx5_tc_flower_es0_tpid()
67 err = vcap_rule_add_key_u32(st->vrule, in sparx5_tc_flower_es0_tpid()
72 err = vcap_rule_add_key_u32(st->vrule, in sparx5_tc_flower_es0_tpid()
77 NL_SET_ERR_MSG_MOD(st->fco->common.extack, in sparx5_tc_flower_es0_tpid()
79 err = -EINVAL; in sparx5_tc_flower_es0_tpid()
91 flow_rule_match_basic(st->frule, &mt); in sparx5_tc_flower_handler_basic_usage()
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Dsparx5_vcap_impl.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
66 .vtype = VCAP_TYPE_IS0, /* CLM-0 */
72 .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1,
73 .blockno = 8, /* Maps block 8-9 */
78 .vtype = VCAP_TYPE_IS0, /* CLM-1 */
84 .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1,
85 .blockno = 6, /* Maps block 6-7 */
90 .vtype = VCAP_TYPE_IS0, /* CLM-2 */
97 .blockno = 4, /* Maps block 4-5 */
[all …]
/linux-6.12.1/drivers/net/dsa/
Dvitesse-vsc73xx-platform.c1 // SPDX-License-Identifier: GPL-2.0
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
8 * This driver takes control of the switch chip connected over CPU-attached
13 * Based on vitesse-vsc-spi.c by:
23 #include "vitesse-vsc73xx.h"
32 * struct vsc73xx_platform - VSC73xx Platform state container
58 struct vsc73xx_platform *vsc_platform = vsc->priv; in vsc73xx_platform_read()
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Dvitesse-vsc73xx-spi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
20 #include "vitesse-vsc73xx.h"
25 #define VSC73XX_CMD_SPI_BLOCK_SHIFT 5
30 * struct vsc73xx_spi - VSC73xx SPI state container
55 struct vsc73xx_spi *vsc_spi = vsc->priv; in vsc73xx_spi_read()
63 return -EINVAL; in vsc73xx_spi_read()
[all …]
Dvitesse-vsc73xx-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
8 * These switches have a built-in 8051 CPU and can download and execute a
10 * handling the switch in a memory-mapped manner by connecting to that external
34 #include "vitesse-vsc73xx.h"
36 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */
40 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Subblocks 0-4, 6, 7 */
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/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
[all …]
/linux-6.12.1/Documentation/hwmon/
Dsparx5-temp.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 Microchip SparX-5 SoC
10 Prefix: 'sparx5-temp'
12 Addresses scanned: -
19 -----------
24 The sensor has a range of -40°C to +125°C and an accuracy of +/-5°C.
27 -------------
/linux-6.12.1/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
[all …]
/linux-6.12.1/drivers/reset/
Dreset-microchip-sparx5.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/reset-controller.h>
42 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in sparx5_switch_reset()
43 ctx->props->protect_bit, ctx->props->protect_bit); in sparx5_switch_reset()
46 regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, in sparx5_switch_reset()
47 ctx->props->reset_bit); in sparx5_switch_reset()
50 return regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val, in sparx5_switch_reset()
51 (val & ctx->props->reset_bit) == 0, in sparx5_switch_reset()
72 syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0); in mchp_sparx5_map_syscon()
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/linux-6.12.1/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
19 bool "Allwinner sunxi 64-bit SoC Family"
40 This enables support for Apple's in-house ARM SoC family, starting
74 Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
77 This enables support for Broadcom BCA ARM-based broadband chipsets,
81 bool "Broadcom Set-Top-Box SoCs"
122 This enables support for the Microchip Sparx5 ARMv8-based
123 SoC family of TSN-capable gigabit switches.
125 The SparX-5 Ethernet switch family provides a rich set of
126 switching features such as advanced TCAM-based VLAN and QoS
[all …]
/linux-6.12.1/drivers/net/phy/
Dvitesse.c1 // SPDX-License-Identifier: GPL-2.0+
71 #define MII_VSC73XX_DOWNSHIFT_MAX 5
78 #define MII_VSC73XX_PBC_PAIR_SWAP_DIS BIT(5)
137 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc824x_config_init()
178 return -E2BIG; in vsc73xx_set_downshift()
180 return -EINVAL; in vsc73xx_set_downshift()
190 cnt - 2); in vsc73xx_set_downshift()
204 switch (tuna->id) { in vsc73xx_get_tunable()
208 return -EOPNOTSUPP; in vsc73xx_get_tunable()
215 switch (tuna->id) { in vsc73xx_set_tunable()
[all …]
/linux-6.12.1/drivers/phy/microchip/
Dsparx5_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
104 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
107 bool no_pwrcycle:1; /* Omit initial power-cycle */
246 bool no_pwrcycle:1; /* Omit initial power-cycle */
522 .cfg_vga_ctrl_3_0 = 5,
624 case 64: return 5; in sd25g28_get_iw_setting()
652 switch (macro->serdesmode) { in sparx5_sd10g25_get_mode_preset()
654 if (macro->speed == SPEED_25000) in sparx5_sd10g25_get_mode_preset()
[all …]
/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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