| /linux-6.12.1/arch/powerpc/xmon/ |
| D | spr_access.S | 34 spr = 0 define
36 mfspr r3, spr
38 spr = spr + 1 define
42 spr = 0 define
44 mtspr spr, r4
46 spr = spr + 1 define
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| D | xmon.c | 284 Sr # read SPR #\n\
285 Sw #v write v to SPR #\n\
349 * write_ciabr() - write the CIABR SPR
525 * We catch SPR read/write faults here because the 0x700, 0xf60 in xmon_core()
1969 extern unsigned long xmon_mfspr(int spr, unsigned long default_value);
1970 extern void xmon_mtspr(int spr, unsigned long value);
2009 printf("SPR 0x%03x (%4d) Faulted during write\n", n, n); in write_spr()
2134 static void dump_one_spr(int spr, bool show_unimplemented) in dump_one_spr() argument
2139 if (!read_spr(spr, &val)) { in dump_one_spr()
2140 printf("SPR 0x%03x (%4d) Faulted during read\n", spr, spr); in dump_one_spr()
[all …]
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| /linux-6.12.1/Documentation/arch/powerpc/ |
| D | dscr.rst | 58 two SPR numbers available for that purpose.
60 (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only)
61 (2) Privileged state SPR: 0x11 (Privileged)
63 Accessing DSCR through privileged SPR number (0x11) from user space
67 Accessing DSCR through user level SPR (0x03) from user space will first
82 (1) mtspr instruction (SPR number 0x03)
83 (2) mtspr instruction (SPR number 0x11)
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| D | dexcr.rst | 10 The DEXCR is a privileged special purpose register (SPR) introduced in
22 A privileged SPR that can control aspects for userspace and kernel space
24 A hypervisor-privileged SPR that can control aspects for the hypervisor and
27 An optional ultravisor-privileged SPR that can control aspects for the ultravisor.
29 Userspace can examine the current DEXCR state using a dedicated SPR that
31 There is also an SPR that provides a read-only view of the hypervisor enforced
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| /linux-6.12.1/tools/testing/selftests/powerpc/dscr/ |
| D | dscr_user_test.c | 3 * POWER Data Stream Control Register (DSCR) SPR test
5 * This test modifies the DSCR value through both the SPR number
7 * reflected through mfspr instruction using either of the SPR
10 * When using the privilege state SPR, the instructions such as
12 * for us. Instructions using problem state SPR can be executed
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| D | dscr_explicit_test.c | 7 * privilege state SPR and the problem state SPR for this purpose.
9 * When using the privilege state SPR, the instructions such as
11 * for us. Instructions using problem state SPR can be executed
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| D | dscr_inherit_test.c | 9 * When using the privilege state SPR, the instructions such as
11 * for us. Instructions using problem state SPR can be executed
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| D | dscr_inherit_exec_test.c | 8 * When using the privilege state SPR, the instructions such as
10 * for us. Instructions using problem state SPR can be executed
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| /linux-6.12.1/drivers/spi/ |
| D | spi-orion.c | 152 * determine the best values for SPR (in [0 .. 15]) and SPPR (in in orion_spi_baudrate_set()
155 * core_clk / (SPR * 2 ** SPPR) in orion_spi_baudrate_set()
162 unsigned spr, sppr; in orion_spi_baudrate_set() local
166 spr = divider; in orion_spi_baudrate_set()
173 * three next bits define SPR (apart from rounding). in orion_spi_baudrate_set()
180 * As SPR only has 4 bits, we have to round divider up in orion_spi_baudrate_set()
190 * doesn't make it into SPR is 0, so there is no need to in orion_spi_baudrate_set()
194 spr = divider >> sppr; in orion_spi_baudrate_set()
197 * Now do range checking. SPR is constructed to have a in orion_spi_baudrate_set()
205 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; in orion_spi_baudrate_set()
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| D | spi-mpc52xx.c | 152 int spr, sppr; in mpc52xx_spi_fsmstate_idle() local
182 spr = 0; in mpc52xx_spi_fsmstate_idle()
187 spr++; in mpc52xx_spi_fsmstate_idle()
190 if (spr > 7) { in mpc52xx_spi_fsmstate_idle()
192 spr = 7; in mpc52xx_spi_fsmstate_idle()
195 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */ in mpc52xx_spi_fsmstate_idle()
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| /linux-6.12.1/arch/powerpc/kernel/ptrace/ |
| D | ptrace-tm.c | 544 * tm_spr_active - get active number of registers in TM SPR
549 * regisers in the transactional memory SPR category.
560 * tm_spr_get - get the TM related SPR registers
565 * This function gets transactional memory related SPR registers.
599 * tm_spr_set - set the TM related SPR registers
607 * This function sets transactional memory related SPR registers.
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| /linux-6.12.1/tools/testing/selftests/powerpc/dexcr/ |
| D | dexcr.c | 31 * If the SPR is not recognised by the hardware it triggers in dexcr_exists()
35 * If we do not receive a signal, assume we have the SPR or the in dexcr_exists()
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 55 0x00800000 /* This state uses SPR PMICR instruction */
110 state if the flag indicates that pmicr SPR should be set. This
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| /linux-6.12.1/tools/testing/selftests/powerpc/ptrace/ |
| D | .gitignore | 11 ptrace-tm-spr
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| D | Makefile | 7 TM_TESTS += ptrace-tm-spr
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| /linux-6.12.1/arch/openrisc/include/asm/ |
| D | timex.h | 19 #include <asm/spr.h>
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| D | smp.h | 12 #include <asm/spr.h>
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| /linux-6.12.1/arch/powerpc/kvm/ |
| D | emulate.c | 118 printk(KERN_INFO "mtspr: unknown spr " in kvmppc_emulate_mtspr()
179 printk(KERN_INFO "mfspr: unknown spr " in kvmppc_emulate_mfspr()
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| /linux-6.12.1/arch/powerpc/kernel/ |
| D | setup.h | 47 /* Default SPR values from firmware/kexec */
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| /linux-6.12.1/drivers/tty/serial/jsm/ |
| D | jsm.h | 262 u8 spr; /* WR SPR - Scratch Pad Reg */ member
317 u8 spr; /* WR SPR - Scratch Pad Reg */ member
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| /linux-6.12.1/arch/openrisc/mm/ |
| D | cache.c | 13 #include <asm/spr.h>
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| /linux-6.12.1/drivers/edac/ |
| D | i10nm_base.c | 251 if (res_cfg->type == SPR) { in show_retry_rd_err_log()
433 * Check whether the error comes from DDRT by ICX/Tremont/SPR model specific error code.
452 case SPR: in i10nm_mscod_is_ddrt()
491 case SPR: in i10nm_mc_decode_available()
540 case SPR: in i10nm_mc_decode()
670 case SPR: in i10nm_imc_absent()
895 .type = SPR,
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| /linux-6.12.1/arch/powerpc/platforms/powernv/ |
| D | idle.c | 48 * First stop state levels when SPR and TB loss can occur.
740 * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so in power9_idle_stop()
741 * just always test PSSCR for SPR/TB state loss. in power9_idle_stop()
945 * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so in power10_idle_stop()
946 * just always test PSSCR for SPR/TB state loss. in power10_idle_stop()
1093 * POWER ISA 3.0 defines a new SPR Processor stop Status and Control
1207 * in a shallower state than SPR loss, so force it to in pnv_arch300_idle_init()
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| D | subcore-asm.S | 75 /* Restore SPR values now we are split */
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| /linux-6.12.1/fs/jffs2/ |
| D | summary.c | 524 struct jffs2_sum_xref_flash *spr; in jffs2_sum_process_sum_data() local
526 spr = (struct jffs2_sum_xref_flash *)sp; in jffs2_sum_process_sum_data()
528 jeb->offset + je32_to_cpu(spr->offset), in jffs2_sum_process_sum_data()
529 jeb->offset + je32_to_cpu(spr->offset) + in jffs2_sum_process_sum_data()
540 sum_link_node_ref(c, jeb, je32_to_cpu(spr->offset) | REF_UNCHECKED, in jffs2_sum_process_sum_data()
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