Searched full:sgis (Results 1 – 24 of 24) sorted by relevance
| /linux-6.12.1/include/kvm/ |
| D | arm_vgic.h | 123 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
149 u8 source; /* GICv2 SGIs only */
150 u8 active_source; /* GICv2 SGIs only */
265 /* Wants SGIs without active state */
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| /linux-6.12.1/arch/arm64/kvm/vgic/ |
| D | vgic-mmio-v3.c | 121 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_write_v3_misc()
131 /* Switching HW SGIs? */ in vgic_mmio_write_v3_misc()
180 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_uaccess_write_v3_misc()
569 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
1029 * An access targeting Group0 SGIs can only generate in vgic_v3_queue_sgi()
1030 * those, while an access targeting Group1 SGIs can in vgic_v3_queue_sgi()
1057 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
1059 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
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| D | vgic.c | 90 /* SGIs and PPIs */ in vgic_get_irq()
595 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
771 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
803 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
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| D | vgic-mmio.c | 323 * GICv2 SGIs are terribly broken. We can't restore in __set_pending()
409 * More fun with GICv2 SGIs! If we're clearing one of them in __clear_pending()
745 * The configuration cannot be changed for SGIs in general, in vgic_mmio_write_config()
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| D | vgic-init.c | 201 * Enable and configure all SGIs to be edge-triggered and in vgic_allocate_private_irqs_locked()
214 /* SGIs */ in vgic_allocate_private_irqs_locked()
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| D | vgic-kvm-device.c | 228 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs in vgic_set_common_attr()
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,omap4-wugen-mpu | 20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
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| D | arm,gic.yaml | 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
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| D | nvidia,tegra20-ictlr.txt | 27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-hip04.c | 122 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
329 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
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| D | irq-gic-common.c | 110 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
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| D | irq-gic-v3.c | 87 * There are 16 SGIs, though we only actually use 8 in Linux. The other 8 SGIs
736 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
989 pr_info("Enabling SGIs without active state\n"); in gic_dist_init()
1262 /* Check all the CPUs have capable of sending SGIs to other CPUs */ in gic_cpu_sys_reg_init()
1317 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1445 /* Register all 8 non-secure SGIs */ in gic_smp_init()
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| D | irq-alpine-msi.c | 35 u32 num_spis; /* The number of SGIs for MSIs */
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| D | irq-gic.c | 297 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
365 * works because we don't nest SGIs... in gic_handle_irq()
1000 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
1007 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
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| D | irq-gic-v3-its.c | 4272 * There is no notion of affinity for virtual SGIs, at least in its_sgi_set_affinity()
4389 /* Yes, we do want 16 SGIs */ in its_sgi_irq_domain_alloc()
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| /linux-6.12.1/tools/testing/selftests/kvm/lib/aarch64/ |
| D | vgic.c | 113 "doesn't allow injecting SGIs. There's no mask for it."); in _kvm_arm_irq_line()
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| D | gic_v3.c | 317 /* Set a default priority for all the SGIs and PPIs */ in gicv3_cpu_init()
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| /linux-6.12.1/drivers/gpio/ |
| D | gpio-xgene-sb.c | 194 /* Skip SGIs and PPIs*/ in xgene_gpio_sb_domain_alloc()
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| /linux-6.12.1/tools/testing/selftests/kvm/aarch64/ |
| D | vgic_irq.c | 536 * The kernel silently fails for invalid SPIs and SGIs (which in kvm_irq_set_level_info_check()
588 * either trying to inject SGIs when we configured the test to be in kvm_irq_write_ispendr_check()
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| /linux-6.12.1/Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.rst | 280 SGIs and any interrupt with a higher ID than the number of interrupts
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| /linux-6.12.1/arch/arm/common/ |
| D | bL_switcher.c | 215 /* redirect GIC's SGIs to our counterpart */ in bL_switch_to()
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| /linux-6.12.1/drivers/soc/xilinx/ |
| D | xlnx_event_manager.c | 585 /* Find GIC controller to map SGIs. */ in xlnx_event_init_sgi()
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| /linux-6.12.1/drivers/mailbox/ |
| D | zynqmp-ipi-mailbox.c | 825 /* Find GIC controller to map SGIs. */ in xlnx_mbox_init_sgi()
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| /linux-6.12.1/arch/arm64/kvm/ |
| D | sys_regs.c | 450 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, in access_gic_sgi()
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