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/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml79 ti,otap-del-sel-sdr12:
80 description: Output tap delay for SD UHS SDR12 timing
149 ti,itap-del-sel-sdr12:
150 description: Input tap delay for SD UHS SDR12 timing
Dcdns,sdhci.yaml51 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the input path for SD UHS SDR12 timing
Dsdhci-omap.txt18 - pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
Dsocionext,uniphier-sd.yaml114 sd-uhs-sdr12;
Dk3-dw-mshc.txt59 sd-uhs-sdr12;
Dmmc-controller.yaml140 sd-uhs-sdr12:
143 SD UHS SDR12 speed is supported.
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-dreambox-one.dts16 sd-uhs-sdr12;
Dmeson-g12b-dreambox-two.dts16 sd-uhs-sdr12;
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dtqmls10xxa.dtsi57 sd-uhs-sdr12;
Dfsl-ls1012a-rdb.dts32 sd-uhs-sdr12;
Dfsl-lx2160a-clearfog-itx.dtsi95 sd-uhs-sdr12;
Dfsl-ls1046a-rdb.dts44 sd-uhs-sdr12;
/linux-6.12.1/arch/riscv/boot/dts/microchip/
Dmpfs-polarberry.dts68 sd-uhs-sdr12;
Dmpfs-sev-kit.dts101 sd-uhs-sdr12;
Dmpfs-m100pfsevp.dts117 sd-uhs-sdr12;
Dmpfs-beaglev-fire.dts167 sd-uhs-sdr12;
Dmpfs-icicle-kit.dts172 sd-uhs-sdr12;
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk3288-veyron-sdmmc.dtsi89 sd-uhs-sdr12;
Drv1126-edgeble-neu2-io.dts102 sd-uhs-sdr12;
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Ddra7-evm.dts389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
420 …pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11…
Ddra72-evm.dts94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
Ddra72-evm-revc.dts124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
/linux-6.12.1/drivers/mmc/host/
Ddw_mmc-k3.c80 {6, 0, 15, 15,}, /* 3: SDR12 */
92 {6, 0, 15, 15,}, /* 3: SDR12 */
Dsdhci-acpi.c628 * a) The clock divisor for SDR12, SDR25, and SDR50 is too small. in sdhci_acpi_emmc_amd_probe_slot()
630 * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 = in sdhci_acpi_emmc_amd_probe_slot()
640 * These presets have proper clock divisors. i.e., SDR12 => 12MHz, in sdhci_acpi_emmc_amd_probe_slot()
657 * firmware that has valid presets (i.e., SDR12 <= 12 MHz). in sdhci_acpi_emmc_amd_probe_slot()
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Dpx30-firefly-jd4-core-mb.dts132 sd-uhs-sdr12;

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