| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rk3288-veyron-sdmmc.dtsi | 3 * Google Veyron (and derivatives) fragment for sdmmc cards
10 mmc1 = &sdmmc;
19 sdmmc {
21 * We run sdmmc at max speed; bump up drive strength.
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
80 &sdmmc {
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| D | rk3288-phycore-rdk.dts | 175 sdmmc {
180 sdmmc_bus4: sdmmc-bus4 {
187 sdmmc_clk: sdmmc-clk {
191 sdmmc_cmd: sdmmc-cmd {
195 sdmmc_pwr: sdmmc-pwr {
223 &sdmmc {
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| D | rk3288-veyron-mighty.dts | 20 &sdmmc {
29 sdmmc {
30 sdmmc_wp_pin: sdmmc-wp-pin {
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| D | rk3288-evb.dtsi | 170 vcc_sd: sdmmc-regulator {
224 &sdmmc {
339 sdmmc {
344 sdmmc_bus4: sdmmc-bus4 {
351 sdmmc_clk: sdmmc-clk {
355 sdmmc_cmd: sdmmc-cmd {
359 sdmmc_pwr: sdmmc-pwr {
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| D | rk3288-firefly-reload.dts | 110 vcc_sd: sdmmc-regulator {
241 &sdmmc {
346 sdmmc {
351 sdmmc_bus4: sdmmc-bus4 {
358 sdmmc_clk: sdmmc-clk {
362 sdmmc_cmd: sdmmc-cmd {
366 sdmmc_pwr: sdmmc-pwr {
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| D | rk3288-miqi.dts | 61 vcc_sd: sdmmc-regulator {
341 sdmmc {
346 sdmmc_bus4: sdmmc-bus4 {
353 sdmmc_clk: sdmmc-clk {
357 sdmmc_cmd: sdmmc-cmd {
361 sdmmc_pwr: sdmmc-pwr {
378 &sdmmc {
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| D | rk3288-tinker.dtsi | 97 vcc_sd: sdmmc-regulator {
407 sdmmc {
408 sdmmc_bus4: sdmmc-bus4 {
415 sdmmc_clk: sdmmc-clk {
419 sdmmc_cmd: sdmmc-cmd {
423 sdmmc_pwr: sdmmc-pwr {
455 &sdmmc {
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| D | rk3288-veyron-pinky.dts | 107 sdmmc {
108 sdmmc_wp_pin: sdmmc-wp-pin {
127 &sdmmc {
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| D | rk3288-firefly.dtsi | 91 vcc_sd: sdmmc-regulator {
440 sdmmc {
445 sdmmc_bus4: sdmmc-bus4 {
452 sdmmc_clk: sdmmc-clk {
456 sdmmc_cmd: sdmmc-cmd {
460 sdmmc_pwr: sdmmc-pwr {
498 &sdmmc {
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| D | rk3288-rock2-square.dts | 120 vcc_sd: sdmmc-regulator {
145 &sdmmc {
244 sdmmc {
245 sdmmc_pwr: sdmmc-pwr {
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| D | rk3288-vmarc-som.dtsi | 292 sdmmc {
293 sdmmc_bus4: sdmmc-bus4 {
301 sdmmc_clk: sdmmc-clk {
305 sdmmc_cmd: sdmmc-cmd {
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| D | rk3066a-mk808.dts | 106 vcc_sd: sdmmc-regulator {
209 sdmmc {
210 sdmmc_pwr: sdmmc-pwr {
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| D | rk3036.dtsi | 27 mshc1 = &sdmmc;
249 sdmmc: mmc@10214000 { label
660 sdmmc {
661 sdmmc_clk: sdmmc-clk {
665 sdmmc_cmd: sdmmc-cmd {
669 sdmmc_cd: sdmmc-cd {
673 sdmmc_bus1: sdmmc-bus1 {
677 sdmmc_bus4: sdmmc-bus4 {
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| /linux-6.12.1/Documentation/devicetree/bindings/mmc/ |
| D | nvidia,tegra20-sdhci.yaml | 228 - const: sdmmc-3v3
230 - const: sdmmc-1v8
232 - const: sdmmc-3v3-drv
234 - const: sdmmc-1v8-drv
237 - const: sdmmc-3v3-drv
239 - const: sdmmc-1v8-drv
242 - const: sdmmc-1v8-drv
257 - const: sdmmc-3v3
259 - const: sdmmc-1v8
296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
[all …]
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| D | synopsys-dw-mshc.yaml | 46 - description: register offset that controls the SDMMC clock phase
50 that contains the SDMMC clock-phase control register. The first value is
52 SDMMC clock phase register, and the 3rd value is the bit shift for the
|
| /linux-6.12.1/drivers/pinctrl/ |
| D | pinctrl-lpc18xx.c | 163 [FUNC_SDMMC] = "sdmmc",
245 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
246 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
247 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
248 LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
250 LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
251 LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
252 LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
253 LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
254 LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
[all …]
|
| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3368-orion-r68-meta.dts | 16 mmc0 = &sdmmc;
273 sdmmc {
274 sdmmc_clk: sdmmc-clk {
278 sdmmc_cmd: sdmmc-cmd {
282 sdmmc_cd: sdmmc-cd {
286 sdmmc_bus1: sdmmc-bus1 {
290 sdmmc_bus4: sdmmc-bus4 {
310 &sdmmc {
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| D | rk3368-lion-haikou.dts | 14 mmc1 = &sdmmc;
71 &sdmmc {
131 sdmmc {
132 sdmmc_cd_pin: sdmmc-cd-pin {
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| D | rk3399-gru.dtsi | 13 mmc0 = &sdmmc;
473 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
536 &sdmmc {
545 * configured as SDMMC and not JTAG.
772 sdmmc {
774 * We run sdmmc at max speed; bump up drive strength.
777 sdmmc_bus4: sdmmc-bus4 {
785 sdmmc_clk: sdmmc-clk {
790 sdmmc_cmd: sdmmc-cmd {
804 sdmmc_cd: sdmmc-cd {
[all …]
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| D | rk3399-rock960.dtsi | 14 mmc1 = &sdmmc;
391 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
430 sdmmc {
431 sdmmc_bus1: sdmmc-bus1 {
436 sdmmc_bus4: sdmmc-bus4 {
444 sdmmc_clk: sdmmc-clk {
449 sdmmc_cmd: sdmmc-cmd {
548 &sdmmc {
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| D | rk3308-roc-cc.dts | 14 mmc0 = &sdmmc;
81 vcc_sdmmc: vcc-sdmmc {
176 &sdmmc {
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| D | rk3399-rock-4c-plus.dts | 19 mmc1 = &sdmmc;
494 sdmmc-supply = <&vcc_sdio_s0>;
543 sdmmc {
544 sdmmc_bus4: sdmmc-bus4 {
551 sdmmc_clk: sdmmc-clk {
555 sdmmc_cmd: sdmmc-cmd {
628 &sdmmc {
|
| /linux-6.12.1/Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 125 SDMMC FIFO ECC
127 - compatible : Should be "altr,socfpga-sdmmc-ecc"
224 sdmmc-ecc@ff8c2c00 {
225 compatible = "altr,socfpga-sdmmc-ecc";
296 SDMMC FIFO ECC
298 - compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
376 sdmmc-ecc@ff8c8c00 {
377 compatible = "altr,socfpga-s10-sdmmc-ecc";
|
| /linux-6.12.1/arch/arm/boot/dts/nxp/lpc/ |
| D | lpc4357-ea4357-devkit.dts | 48 /* vmmc is controlled by sdmmc host internally */
348 sdmmc_pins: sdmmc-pins {
351 function = "sdmmc";
358 function = "sdmmc";
367 function = "sdmmc";
374 function = "sdmmc";
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| /linux-6.12.1/drivers/mmc/host/ |
| D | mmci.h | 24 * The STM32 sdmmc does not have PWR_UP/OD/ROD
58 /* Modified on STM32 sdmmc */
93 /* Command register in STM32 sdmmc versions */
222 /* STM32 sdmmc data FIFO threshold register */
229 /* STM32 sdmmc registers for IDMA (Internal DMA) */
335 * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
|