| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | rockchip,rk3576-cru.yaml | 16 controller for SoC peripherals. For example it provides SCLK_UART2 and
|
| D | rockchip,rk3588-cru.yaml | 15 controller for SoC peripherals. For example it provides SCLK_UART2 and
|
| D | samsung,exynos7-clock.yaml | 153 - const: sclk_uart2
|
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | rk3036-cru.h | 25 #define SCLK_UART2 79 macro
|
| D | exynos7-clk.h | 97 #define SCLK_UART2 5 macro
|
| D | s5pv210.h | 195 #define SCLK_UART2 173 macro
|
| D | rk3188-cru-common.h | 22 #define SCLK_UART2 66 macro
|
| D | rk3228-cru.h | 26 #define SCLK_UART2 79 macro
|
| D | rk3128-cru.h | 27 #define SCLK_UART2 79 macro
|
| D | rv1108-cru.h | 24 #define SCLK_UART2 74 macro
|
| D | rk3308-cru.h | 23 #define SCLK_UART2 19 macro
|
| D | rk3368-cru.h | 32 #define SCLK_UART2 79 macro
|
| D | rk3288-cru.h | 34 #define SCLK_UART2 79 macro
|
| D | rk3328-cru.h | 29 #define SCLK_UART2 40 macro
|
| D | px30-cru.h | 27 #define SCLK_UART2 25 macro
|
| D | rockchip,rk3576-cru.h | 159 #define SCLK_UART2 141 macro
|
| D | rockchip,rv1126-cru.h | 86 #define SCLK_UART2 20 macro
|
| D | rockchip,rk3588-cru.h | 190 #define SCLK_UART2 175 macro
|
| D | rk3399-cru.h | 40 #define SCLK_UART2 83 macro
|
| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 158 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
|
| D | clk-rk3128.c | 194 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
|
| /linux-6.12.1/arch/arm64/boot/dts/exynos/ |
| D | exynos7.dtsi | 236 "sclk_uart2",
307 <&clock_peric1 SCLK_UART2>;
|
| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-exynos7.c | 361 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
706 PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
780 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
|
| D | clk-exynos5410.c | 219 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
|
| D | clk-s5pv210.c | 596 GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
|