Home
last modified time | relevance | path

Searched full:sclk_i2s1 (Results 1 – 25 of 25) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/sound/
Drockchip,rk3328-codec.yaml68 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
/linux-6.12.1/include/dt-bindings/clock/
Dexynos7-clk.h117 #define SCLK_I2S1 25 macro
Drk3188-cru-common.h32 #define SCLK_I2S1 76 macro
Drk3228-cru.h28 #define SCLK_I2S1 81 macro
Drk3128-cru.h29 #define SCLK_I2S1 81 macro
Drv1108-cru.h26 #define SCLK_I2S1 76 macro
Drk3328-cru.h31 #define SCLK_I2S1 42 macro
Dpx30-cru.h22 #define SCLK_I2S1 20 macro
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsamsung,exynos7-clock.yaml160 - const: sclk_i2s1
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynos7.c347 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
794 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
Dclk-exynos4.c641 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
Dclk-exynos5420.c1004 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
Dclk-exynos5433.c1731 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
/linux-6.12.1/drivers/clk/rockchip/
Dclk-rk3128.c368 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
Dclk-rk3228.c434 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
Dclk-rv1108.c521 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
Dclk-rk3188.c551 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
Dclk-rk3328.c387 GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
Dclk-px30.c638 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk3066a.dtsi198 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
Drk322x.dtsi144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
Drk3128.dtsi513 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>;
/linux-6.12.1/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi243 "sclk_i2s1",
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3328.dtsi258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
793 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
Dpx30.dtsi414 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;