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/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a73a4.dtsi525 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
532 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
539 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
546 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
553 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
560 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
567 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
575 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
583 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
591 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
[all …]
/linux-6.12.1/include/dt-bindings/clock/
Dr8a73a4-clock.h14 #define R8A73A4_CLK_PLL2S 4 macro
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Drenesas,cpg-div6-clock.yaml69 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,