Searched +full:quad +full:- +full:usgmii (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Horatiu Vultur <horatiu.vultur@microchip.com>13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to16 2 Quad-SGMII/Quad-USGMII interfaces.20 pattern: "^switch@[0-9a-f]+$"[all …]
26 #. Increase code-reuse27 #. Increase overall code-maintainability67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin84 or the PCB traces insert the correct 1.5-2ns delay97 * PHY devices may offer sub-nanosecond granularity in how they allow a115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are130 -----------------------------------------197 PHY-specific flags should be set in phydev->dev_flags prior to the call208 Now just make sure that phydev->supported and phydev->advertising have any[all …]