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/linux-6.12.1/Documentation/hwmon/
Dbcm54140.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 Broadcom BCM54140 Quad SGMII/QSGMII PHY
15 -----------
17 The Broadcom BCM54140 is a Quad SGMII/QSGMII PHY which supports monitoring
21 Both voltages and the temperature are measured in a round-robin fashion.
24 -------------
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
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/linux-6.12.1/drivers/net/ethernet/qualcomm/emac/
Demac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
12 #include "emac-mac.h"
13 #include "emac-phy.h"
14 #include "emac-sgmii.h"
176 /* SGMII v2 per lane registers */
179 /* SGMII v2 PHY common registers */
183 /* SGMII v2 PHY registers per lane */
225 u64 rx_sz_65_127; /* packets that are 65-127 bytes */
226 u64 rx_sz_128_255; /* packets that are 128-255 bytes */
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/linux-6.12.1/arch/arm/boot/dts/nxp/ls/
Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
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/linux-6.12.1/drivers/net/phy/
Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
13 #include "bcm-phy-lib.h"
15 /* RDB per-port registers
60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
80 * T = 413.35 - (0.49055 * bits[9:0])
82 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
83 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
119 * pin choses between 4x SGMII and QSGMII mode:
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 Adds support for a set of LED trigger events per-PHY. Link
39 logical-or of all the link speed ones.
64 Currently tested with mpc866ads and mpc8349e-mitx.
104 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
105 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
113 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
127 Currently supports the Asix Electronics PHY found in the X-Surf 100
136 found in the X-Surf 100 AX88796B package.
152 Support the Broadcom BCM54140 Quad SGMII/QSGMII PHY.
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/linux-6.12.1/Documentation/networking/
Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
205 RGMII, and SGMII. See "PHY interface mode" below. For a full
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/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-8040-puzzle-m801.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Device Tree file for IEI Puzzle-M801
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/leds/common.h>
15 model = "IEI-Puzzle-M801";
16 compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806";
28 stdout-path = "serial0:115200n8";
37 v_3_3: regulator-3-3v {
38 compatible = "regulator-fixed";
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Darmada-7040-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-7040.dtsi"
13 compatible = "marvell,armada7040-db", "marvell,armada7040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
31 cp0_exp_usb3_0_current_regulator: gpio-regulator {
32 compatible = "regulator-gpio";
33 regulator-name = "cp0-usb3-0-current-regulator";
34 regulator-type = "current";
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Darmada-8040-mcbin.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
15 "marvell,armada-ap806-quad", "marvell,armada-ap806";
18 stdout-path = "serial0:115200n8";
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
37 regulator-min-microvolt = <3300000>;
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Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1028a.dtsi"
16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
38 stdout-path = "serial0:115200n8";
46 sys_mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <25000000>;
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/linux-6.12.1/include/linux/
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
82 * Set phydev->irq to PHY_POLL if interrupts are not supported,
86 #define PHY_POLL -1
87 #define PHY_MAC_INTERRUPT -2
96 * enum phy_interface_t - Interface Mode definitions
98 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
100 * @PHY_INTERFACE_MODE_MII: Media-independent interface
101 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
102 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
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/linux-6.12.1/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x()
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw()
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
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/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
89 * ice_dump_phy_type - helper function to dump phy_type
116 * ice_set_mac_type - Sets MAC type
124 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
125 return -ENODEV; in ice_set_mac_type()
127 switch (hw->device_id) { in ice_set_mac_type()
134 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
155 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
161 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
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