Home
last modified time | relevance | path

Searched full:polarfire (Results 1 – 25 of 37) sorted by relevance

12

/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dmicrochip,mpfs-clkcfg.yaml7 title: Microchip PolarFire Clock Control Module
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
45 PolarFire clock IDs.
52 The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
56 PolarFire clock IDs.
Dmicrochip,mpfs-ccc.yaml7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
15 the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
58 PolarFire clock IDs.
/linux-6.12.1/drivers/clk/microchip/
DKconfig7 bool "Clk driver for PolarFire SoC"
12 Supports Clock Configuration for PolarFire SoC
Dclk-mpfs.c3 * PolarFire SoC MSS/core complex clock control
103 * The only two supported reference clock frequencies for the PolarFire SoC are
442 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
/linux-6.12.1/drivers/soc/microchip/
DKconfig2 tristate "Microchip PolarFire SoC (MPFS) system controller support"
6 This driver adds support for the PolarFire SoC (MPFS) system controller.
/linux-6.12.1/drivers/firmware/microchip/
DKconfig4 tristate "Microchip PolarFire SoC AUTO UPDATE"
9 Support for reprogramming PolarFire SoC from within Linux, using the
Dmpfs-auto-update.c3 * Microchip Polarfire SoC "Auto Update" FPGA reprogramming.
5 * Documentation of this functionality is available in the "PolarFire® FPGA and
6 * PolarFire SoC FPGA Programming" User Guide.
467 MODULE_DESCRIPTION("PolarFire SoC Auto Update FPGA reprogramming");
/linux-6.12.1/Documentation/devicetree/bindings/riscv/
Dmicrochip.yaml7 title: Microchip PolarFire SoC-based boards
14 Microchip PolarFire SoC-based boards
/linux-6.12.1/Documentation/devicetree/bindings/fpga/
Dmicrochip,mpf-spi-fpga-mgr.yaml7 title: Microchip Polarfire FPGA manager.
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dmicrochip,mfps-rtc.yaml8 title: Microchip PolarFire Soc (MPFS) RTC
40 on the PolarFire SoC shares it's reference with MTIMER so this will
/linux-6.12.1/Documentation/devicetree/bindings/soc/microchip/
Dmicrochip,mpfs-sys-controller.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
13 PolarFire SoC devices include a microcontroller acting as the system controller,
/linux-6.12.1/drivers/char/hw_random/
Dmpfs-rng.c3 * Microchip PolarFire SoC (MPFS) hardware random driver
101 MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dmicrochip,pcie-host.yaml18 const: microchip,pcie-host-1.0 # PolarFire
23 fabric and the core complex on PolarFire SoC. The FICs require two clocks,
/linux-6.12.1/drivers/usb/musb/
DKconfig115 tristate "Microchip PolarFire SoC platforms"
120 Say Y here to enable support for USB on Microchip's PolarFire SoC.
Dmpfs.c3 * PolarFire SoC (MPFS) MUSB Glue Layer
100 * We poll because PolarFire SoC won't expose several OTG-critical in otg_timer()
381 MODULE_DESCRIPTION("PolarFire SoC MUSB Glue Layer");
/linux-6.12.1/drivers/fpga/
Dmicrochip-spi.c3 * Microchip Polarfire FPGA programming over slave SPI interface.
379 mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager", in mpf_probe()
410 MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
DKconfig273 tristate "Microchip Polarfire SPI FPGA manager"
276 FPGA manager driver support for Microchip Polarfire FPGAs
/linux-6.12.1/drivers/reset/
Dreset-mpfs.c3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
232 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
DKconfig191 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
196 This driver supports peripheral reset for the Microchip PolarFire SoC
/linux-6.12.1/Documentation/devicetree/bindings/net/can/
Dmicrochip,mpfs-can.yaml8 Microchip PolarFire SoC (MPFS) can controller
/linux-6.12.1/include/soc/microchip/
Dmpfs.h4 * Microchip PolarFire SoC (MPFS)
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dmicrochip,corei2c.yaml19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
/linux-6.12.1/Documentation/devicetree/bindings/mailbox/
Dmicrochip,mpfs-mailbox.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dmicrochip,mpfs-spi.yaml10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
/linux-6.12.1/drivers/mailbox/
DKconfig169 tristate "PolarFire SoC (MPFS) Mailbox"
173 This driver adds support for the PolarFire SoC (MPFS) mailbox controller.

12