Searched full:ppis (Results 1 – 25 of 28) sorted by relevance
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| /linux-6.12.1/drivers/perf/ |
| D | arm_pmu_acpi.c | 49 * a fixed value in HW (for both SPIs and PPIs) that we cannot change in arm_pmu_acpi_register_irq()
238 * corresponding GSI once (e.g. when we have PPIs). in arm_pmu_acpi_parse_irqs()
268 * the PMU (e.g. we don't have mismatched PPIs).
288 pr_warn("mismatched PPIs detected\n"); in pmu_irq_matches()
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| D | arm_pmu_platform.c | 134 dev_warn(dev, "multiple PPIs or mismatched SPI/PPI detected\n"); in pmu_parse_irqs()
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| D | arm_spe_pmu.c | 1159 /* Request our PPIs (note that the IRQ is still disabled) */ in arm_spe_pmu_dev_init()
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,omap4-wugen-mpu | 20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
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| D | arm,gic.yaml | 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
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| D | nvidia,tegra20-ictlr.txt | 27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
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| D | arm,gic-v3.yaml | 63 interrupt types other than PPI or PPIs that are not partitioned,
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| /linux-6.12.1/drivers/acpi/arm64/ |
| D | gtdt.c | 86 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
90 * So we only handle the non-secure timer PPIs,
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| /linux-6.12.1/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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| /linux-6.12.1/drivers/clocksource/ |
| D | timer-mediatek-cpux.c | 87 * on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
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| /linux-6.12.1/arch/arm64/kvm/ |
| D | arch_timer.c | 1454 u32 ppis = 0; in timer_irqs_are_valid() local
1469 * We know by construction that we only have PPIs, so in timer_irqs_are_valid()
1472 ppis |= BIT(irq); in timer_irqs_are_valid()
1475 valid = hweight32(ppis) == nr_timers(vcpu); in timer_irqs_are_valid()
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| /linux-6.12.1/arch/arm64/kvm/vgic/ |
| D | vgic.c | 90 /* SGIs and PPIs */ in vgic_get_irq()
410 * @vcpu: The CPU for PPIs or NULL for global interrupts
579 * @vcpu: Pointer to the VCPU (used for PPIs)
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| D | vgic-init.c | 202 * configure all PPIs as level-triggered. in vgic_allocate_private_irqs_locked()
218 /* PPIs */ in vgic_allocate_private_irqs_locked()
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| D | vgic-mmio.c | 746 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer in vgic_mmio_write_config()
747 * code relies on PPIs being level triggered, so we also in vgic_mmio_write_config()
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| D | vgic-kvm-device.c | 228 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs in vgic_set_common_attr()
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| D | vgic-mmio-v3.c | 569 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
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| /linux-6.12.1/drivers/gpio/ |
| D | gpio-xgene-sb.c | 194 /* Skip SGIs and PPIs*/ in xgene_gpio_sb_domain_alloc()
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| /linux-6.12.1/tools/testing/selftests/kvm/lib/aarch64/ |
| D | gic_v3.c | 317 /* Set a default priority for all the SGIs and PPIs */ in gicv3_cpu_init()
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-hip04.c | 135 /* Misconfigured PPIs are usually not fatal */ in hip04_irq_set_type()
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| D | irq-gic-v3.c | 754 /* Misconfigured PPIs are usually not fatal */ in gic_set_type()
1152 pr_info("GICv3 features: %d PPIs%s%s\n", in gic_update_rdist_properties()
1317 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1660 * Partitioned PPIs are an unfortunate exception. in gic_irq_domain_translate()
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| /linux-6.12.1/tools/testing/selftests/kvm/aarch64/ |
| D | vgic_irq.c | 97 /* can inject PPIs, PPIs, and/or SPIs. */
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| /linux-6.12.1/include/kvm/ |
| D | arm_vgic.h | 123 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
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| /linux-6.12.1/Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.rst | 284 PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
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| /linux-6.12.1/drivers/net/hyperv/ |
| D | hyperv_net.h | 939 u8 ppi_flags; /* valid/present bits for the above PPIs */
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| D | rndis_filter.c | 410 /* Copy the PPIs into nvchan->recv_buf */ in rndis_get_ppi()
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