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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dphy-rockchip-naneng-combphy.yaml133 <&cru PCLK_PIPEPHY0>,
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi259 <&cru PCLK_PIPEPHY0>,
/linux-6.12.1/include/dt-bindings/clock/
Drk3568-cru.h444 #define PCLK_PIPEPHY0 380 macro
/linux-6.12.1/drivers/clk/rockchip/
Dclk-rk3568.c1452 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,