| /linux-6.12.1/drivers/bcma/ |
| D | driver_pcie2.c | 20 static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
22 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
23 pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
24 return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
28 static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr, in bcma_core_pcie2_cfg_write() argument
31 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr); in bcma_core_pcie2_cfg_write()
32 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val); in bcma_core_pcie2_cfg_write()
39 static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2, in bcma_core_pcie2_war_delay_perst_enab() argument
45 val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL); in bcma_core_pcie2_war_delay_perst_enab()
52 pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val); in bcma_core_pcie2_war_delay_perst_enab()
[all …]
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| D | bcma_private.h | 142 void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
143 void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2);
145 static inline void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2) in bcma_core_pcie2_init() argument
148 WARN_ON(pcie2->core->bus->hosttype == BCMA_HOSTTYPE_PCI); in bcma_core_pcie2_init()
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| /linux-6.12.1/include/linux/bcma/ |
| D | bcma_driver_pcie2.h | 151 #define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset) argument
152 #define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset) argument
153 #define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val) argument
154 #define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val) argument
156 #define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set) argument
157 #define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask) argument
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | qcom,pcie2-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
7 title: Qualcomm PCIe2 PHY controller
13 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
19 - const: qcom,qcs404-pcie2-phy
20 - const: qcom,pcie2-phy
71 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
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| D | transmit-amplitude.yaml | 55 - pcie2
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| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3588-edgeble-neu6a-wifi.dtso | 47 pcie2 {
48 pcie2_1_rst: pcie2-1-rst {
52 pcie2_1_vcc3v3_en: pcie2-1-vcc-en {
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| D | rk3588-edgeble-neu6a-io.dtsi | 123 pcie2 {
124 pcie2_0_rst: pcie2-0-rst {
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| D | rk3588-ok3588-c.dts | 316 pcie2 {
317 pcie2_0_rst: pcie2-0-rst {
321 pcie2_2_rst: pcie2-2-rst {
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| D | rk3588-rock-5b.dts | 366 pcie2 {
367 pcie2_0_rst: pcie2-0-rst {
371 pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
375 pcie2_2_rst: pcie2-2-rst {
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| D | rk3588s-khadas-edge2.dts | 243 pcie2 {
244 pcie2_2_rst: pcie2-2-rst {
248 pcie2_2_vcc3v3_en: pcie2-2-vcc-en {
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| /linux-6.12.1/arch/arm/boot/dts/marvell/ |
| D | armada-388-clearfog.dts | 79 pcie2-0-clkreq-hog {
83 line-name = "pcie2.0-clkreq";
85 pcie2-0-w-disable-hog {
89 line-name = "pcie2.0-w-disable";
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| /linux-6.12.1/arch/arm64/boot/dts/marvell/ |
| D | cn9130-cf.dtsi | 59 pcie2-0-clkreq-hog {
63 line-name = "pcie2.0-clkreq";
67 pcie2-0-w-disable-hog {
71 line-name = "pcie2.0-w-disable";
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| D | armada-8040-db.dts | 114 phy-names = "cp0-pcie2-x1-phy";
229 phy-names = "cp1-pcie2-x1-phy";
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| /linux-6.12.1/arch/sh/drivers/pci/ |
| D | pcie-sh7786.c | 92 .name = "PCIe2 MEM 0",
97 .name = "PCIe2 MEM 1",
102 .name = "PCIe2 MEM 2",
107 .name = "PCIe2 IO",
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/marvell/ |
| D | cp110-system-controller.txt | 97 mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), ua…
119 mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), …
124 …io(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1
127 … ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5
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| /linux-6.12.1/arch/arm64/boot/dts/ti/ |
| D | k3-j784s4.dtsi | 243 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
256 <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
258 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
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| /linux-6.12.1/Documentation/admin-guide/perf/ |
| D | nvidia-pmu.rst | 230 | |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
248 PCIE2 traffic represents reads and relaxed ordered (RO) writes.
287 | | PCI R/W | CPU | CPU/PCIE1| PCIE2 |
299 PCIE2 traffic represents reads and relaxed ordered (RO) writes.
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| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-38x-pinctrl.txt | 31 … 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq)
76 mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(…
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| D | marvell,armada-39x-pinctrl.txt | 31 mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data)
80 mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
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| /linux-6.12.1/arch/arm/boot/dts/broadcom/ |
| D | bcm-nsp-ax.dtsi | 68 &pcie2 {
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| /linux-6.12.1/arch/arm/boot/dts/qcom/ |
| D | qcom-ipq8064-v2.0.dtsi | 51 &pcie2 {
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| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | Makefile | 8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
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| D | phy-qcom-pcie2.c | 316 { .compatible = "qcom,pcie2-phy" },
324 .name = "phy-qcom-pcie2",
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| /linux-6.12.1/drivers/pinctrl/mvebu/ |
| D | pinctrl-armada-cp110.c | 116 MPP_FUNCTION(7, "pcie2", "clkreq"),
264 MPP_FUNCTION(6, "pcie2", "clkreq"),
323 MPP_FUNCTION(9, "pcie2", "clkreq"),
358 MPP_FUNCTION(9, "pcie2", "clkreq"),
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| /linux-6.12.1/drivers/interconnect/imx/ |
| D | imx8mq.c | 78 DEFINE_BUS_MASTER("PCIE2", IMX8MQ_ICM_PCIE2, IMX8MQ_ICN_MAIN),
|