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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8ulp.dtsi227 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
236 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
237 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
248 pcc3: clock-controller@292d0000 { label
249 compatible = "fsl,imx8ulp-pcc3";
291 clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
292 <&pcc3 IMX8ULP_CLK_TPM5>;
301 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
302 <&pcc3 IMX8ULP_CLK_LPI2C4>;
304 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7ulp.dtsi299 pcc3: clock-controller@40b30000 { label
300 compatible = "fsl,imx7ulp-pcc3";
332 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>,
335 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
345 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>,
348 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
358 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
360 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
370 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
372 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dimx8ulp-pcc-clock.yaml21 - fsl,imx8ulp-pcc3
46 compatible = "fsl,imx8ulp-pcc3";
Dimx7ulp-pcc-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
41 - fsl,imx7ulp-pcc3
Dimx7ulp-scg-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
/linux-6.12.1/include/dt-bindings/reset/
Dimx8ulp-pcc-reset.h9 /* PCC3 */
/linux-6.12.1/include/dt-bindings/clock/
Dimx7ulp-clock.h94 /* PCC3 */
Dimx8ulp-clock.h119 /* PCC3 */
/linux-6.12.1/drivers/clk/imx/
Dclk-imx7ulp.c197 /* PCC3 */ in imx7ulp_clk_pcc3_init()
228 CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
Dclk-imx8ulp.c327 /* PCC3 */ in imx8ulp_clk_pcc3_init()
390 /* register the pcc3 reset controller */ in imx8ulp_clk_pcc3_init()
549 { .compatible = "fsl,imx8ulp-pcc3", .data = imx8ulp_clk_pcc3_init },
/linux-6.12.1/drivers/pinctrl/tegra/
Dpinctrl-tegra210.c334 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"),
Dpinctrl-tegra30.c519 PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),