Searched full:mx8qm (Results 1 – 25 of 32) sorted by relevance
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| /linux-6.12.1/drivers/gpu/drm/bridge/imx/ |
| D | Kconfig | 25 tristate "Freescale i.MX8QM LVDS display bridge"
32 Freescale i.MX8qm processor. Official name of LDB is pixel mapper.
45 tristate "Freescale i.MX8QM/QXP pixel combiner"
51 Freescale i.MX8qm/qxp processors.
54 tristate "Freescale i.MX8QM/QXP display pixel link"
60 Freescale i.MX8qm/qxp processors.
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| D | imx8qxp-pixel-combiner.c | 440 MODULE_DESCRIPTION("i.MX8QM/QXP pixel combiner bridge driver");
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| /linux-6.12.1/Documentation/devicetree/bindings/display/bridge/ |
| D | fsl,imx8qxp-ldb.yaml | 7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
33 A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
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| D | fsl,imx8qxp-pixel-link.yaml | 7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
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| D | fsl,imx8qxp-pixel-combiner.yaml | 7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
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| /linux-6.12.1/drivers/phy/freescale/ |
| D | Kconfig | 18 on NXP's i.MX8qm SoC.
39 tristate "Freescale i.MX8QM HSIO PHY"
44 i.MX8QM family of SOCs.
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| D | phy-fsl-imx8qm-hsio.c | 143 * On i.MX8QM, only second or third lane can be in imx_hsio_init()
164 /* On i.MX8QM, only the third lane can be bound to SATA */ in imx_hsio_init()
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8qm-lvds-phy.yaml | 7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
23 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
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| D | fsl,imx8qm-hsio.yaml | 7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
50 Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
53 | | i.MX8QM |
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| /linux-6.12.1/Documentation/devicetree/bindings/ata/ |
| D | imx-sata.yaml | 67 Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
71 - description: phandle to the first lane PHY of i.MX8QM.
72 - description: phandle to the second lane PHY of i.MX8QM.
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| /linux-6.12.1/drivers/firmware/imx/ |
| D | Kconfig | 8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
20 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
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| D | imx-scu-soc.c | 85 return "i.MX8QM"; in imx_scu_soc_name()
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| /linux-6.12.1/Documentation/devicetree/bindings/mfd/ |
| D | fsl,imx8qxp-csr.yaml | 7 title: Freescale i.MX8qm/qxp Control and Status Registers Module
13 As a system controller, the Freescale i.MX8qm/qxp Control and Status
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | amphion,vpu.yaml | 53 separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
110 # Device node example for i.MX8QM platform:
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| /linux-6.12.1/Documentation/devicetree/bindings/bus/ |
| D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 24 Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
28 The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
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| /linux-6.12.1/drivers/media/platform/nxp/imx-jpeg/ |
| D | mxc-jpeg.h | 3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
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| D | mxc-jpeg-hw.h | 3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
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| D | mxc-jpeg-hw.c | 3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
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| /linux-6.12.1/drivers/net/can/flexcan/ |
| D | flexcan.h | 30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
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| /linux-6.12.1/Documentation/devicetree/bindings/firmware/ |
| D | fsl,scu.yaml | 15 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
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| /linux-6.12.1/drivers/pinctrl/freescale/ |
| D | pinctrl-imx8qm.c | 333 MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
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| /linux-6.12.1/drivers/remoteproc/ |
| D | imx_dsp_rproc.c | 275 /* Specific configuration for i.MX8QM */
948 * On i.MX8QM and i.MX8QXP there is multiple power domains
971 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
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| /linux-6.12.1/sound/soc/fsl/ |
| D | fsl_mqs.c | 204 * But in i.MX8QM/i.MX8QXP the control register is moved in fsl_mqs_probe()
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| D | fsl_asrc.c | 77 * i.MX8QM/i.MX8QXP uses the same map for input and output.
78 * clk_map_imx8qm[0] is for i.MX8QM asrc0
79 * clk_map_imx8qm[1] is for i.MX8QM asrc1
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | fsl.yaml | 1222 - description: i.MX8QM based Boards
1225 - fsl,imx8qm-mek # i.MX8QM MEK Board
1230 - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
1239 - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
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