Searched full:mtu2 (Results 1 – 22 of 22) sorted by relevance
4 $id: http://devicetree.org/schemas/timer/renesas,mtu2.yaml#7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs18 independent. The MTU2 hardware supports five channels indexed from 0 to 4.24 - renesas,mtu2-r7s72100 # RZ/A1H25 - const: renesas,mtu268 mtu2: timer@fcff0000 {69 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
18 for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination35 - [MTU1, MTU2]38 of MTU1 and MTU2 (when TMDR3.LWA = 1)56 - [MTU0/MTU5, MTU1, MTU2, and MTU8]57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase77 counting mode in which MTU1 and MTU2 are cascaded.84 count1 - MTU2 16-bit phase counting85 count2 - MTU1+ MTU2 32-bit phase counting98 pwm3 - MTU2.MTIOC2A PWM mode 1[all …]
45 …(g)?ether(avb)?|gpio|hscif|(r)?i[i2]c|imr|intc|ipmmu|irqc|jpu|mmcif|msiof|mtu2|pci(e)?|pfc|pwm|[rq…53 - renesas,mtu2-r7s72100
97 [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */126 CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
133 [MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */160 CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
366 .name = "sh-mtu2",413 /* enable MTU2 clock */ in plat_early_device_setup()
285 .name = "sh-mtu2",350 /* enable MTU2 clock */ in plat_early_device_setup()
123 .name = "sh-mtu2",
286 /* enable MTU2 clock */ in plat_early_device_setup()
467 .name = "sh-mtu2",
445 .name = "sh-mtu2",
3 * SuperH Timer Support - MTU2488 { "sh-mtu2", 0 },494 { .compatible = "renesas,mtu2" },527 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
531 bool "Renesas MTU2 timer driver" if COMPILE_TEST536 Timer Pulse Unit 2 (MTU2) hardware available on SoCs from Renesas.
336 MTU2, enumerator428 INTC_VECT(MTU2, 0xE20),473 MTU2,523 { MTU2, RGPVG, MIMLB, IEBUS } },
64 clk_add_alias("fck", "sh-mtu2", "peripheral_clk", NULL); in cpg_clk_init()
39 * LWA: MTU1/MTU2 Combination Longword Access Control436 * 32-bit phase counting need MTU1 and MTU2 to create 32-bit in rz_mtu3_initialize_counter()713 RZ_MTU3_PHASE_SIGNAL(SIGNAL_C_ID, "MTU2 MTCLKC"),714 RZ_MTU3_PHASE_SIGNAL(SIGNAL_D_ID, "MTU2 MTCLKD"),
429 clock-output-names = "mtu2";716 mtu2: timer@fcff0000 { label717 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
97 &mtu2 {
178 &mtu2 {
245 &mtu2 {
54 mtu2-pwm {
85 * and MTU2 channel is 1 compared to 2 on others.