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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
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Dplda,xpressrich3-axi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
11 - Kevin Xie <kevin.xie@starfivetech.com>
17 - $ref: /schemas/pci/pci-host-bridge.yaml#
23 reg-names:
25 - const: cfg
26 - const: apb
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Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dmarvell,xor-v2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
19 - const: marvell,xor-v2
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/linux-6.12.1/drivers/ata/
Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
82 HOST_MRSM = BIT(2), /* MSI Revert to Single Message */
89 HOST_CAP_PART = BIT(13), /* Partial state capable */
90 HOST_CAP_SSC = BIT(14), /* Slumber state capable */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
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/linux-6.12.1/drivers/pci/msi/
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
15 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
37 if (!dev || dev->no_msi) in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
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Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
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/linux-6.12.1/drivers/pci/controller/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
30 This MSI driver supports Altera MSI to GIC controller IP.
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
93 bool "Broadcom iProc PCIe MSI support"
98 Say Y here if you want to enable MSI support for Broadcom's iProc
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
20 #include <linux/msi.h>
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
169 /* MSI target addresses */
194 #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
195 #define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA])
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/linux-6.12.1/include/uapi/linux/
Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
88 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
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/linux-6.12.1/Documentation/PCI/
Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
47 - Set the DMA mask size (for both coherent and streaming DMA)
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/linux-6.12.1/Documentation/PCI/endpoint/
Dpci-endpoint.rst1 .. SPDX-License-Identifier: GPL-2.0
15 vendor ID, device ID), support other services like hot-plug, power management,
18 However the PCI controller IP integrated in some SoCs is capable of operating
22 validation, co-processor accelerator, etc.
32 ------------------------------------
53 * raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
107 Legacy Interrupt, MSI or MSI-X Interrupt.
124 the EPF device with EPC device. pci-ep-cfs.c can be used as reference for
158 ----------------------------------
212 pci-ep-cfs.c can be used as reference for using these APIs.
/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-bus-pci4 Contact: linux-pci@vger.kernel.org
15 (Note: kernels before 2.6.28 may require echo -n).
20 Contact: linux-pci@vger.kernel.org
31 (Note: kernels before 2.6.28 may require echo -n).
36 Contact: linux-pci@vger.kernel.org
55 Contact: Chris Wright <chrisw@sous-sol.org>
72 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
74 Writing a non-zero value to this attribute will
76 re-discover previously removed devices.
80 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
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/linux-6.12.1/include/xen/interface/
Dphysdev.h1 /* SPDX-License-Identifier: MIT */
10 * @args == Operation-specific extra arguments (NULL if none).
14 * Notify end-of-interrupt (EOI) for the specified IRQ.
75 * Set the current VCPU's I/O-port permissions bitmap.
86 * Read or write an IO-APIC register.
127 /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
132 * - For MSI-X contains entry number.
133 * - For MSI with ..._MULTI_MSI contains number of vectors.
135 * - Number of vectors allocated.
255 * MSI-X capable devices won't (prepare) or may (release) change.
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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/linux-6.12.1/include/linux/
Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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/linux-6.12.1/Documentation/accel/qaic/
Daic100.rst1 .. SPDX-License-Identifier: GPL-2.0-only
10 The Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of
15 The PCIe interface of AIC100 is capable of PCIe Gen4 speeds over eight lanes
20 performance. AIC100 cards are multi-user capable and able to execute workloads
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
40 operate (1 for MHI, 16 for the DMA Bridge). Falling back to 1 MSI is possible in
44 hardware. AIC100 provides 3, 64-bit BARs.
54 From the host perspective, AIC100 has several key hardware components -
63 ---
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/linux-6.12.1/Documentation/arch/x86/
Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
71 that sets up the routing for DMA and page-requests.
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/linux-6.12.1/drivers/net/ethernet/chelsio/cxgb3/
Dcxgb3_main.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
120 * msi = 2: choose from among all three options
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/linux-6.12.1/drivers/pci/
Dpci-sysfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2002-2004 Greg Kroah-Hartman <greg@kroah.com>
4 * (C) Copyright 2002-2004 IBM Corp.
6 * (C) Copyright 2003 Hewlett-Packard
29 #include <linux/msi.h>
48 return sysfs_emit(buf, format_string, pdev->field); \
67 * For MSI, show the first MSI IRQ; for all other cases including in irq_show()
68 * MSI-X, show the legacy INTx IRQ. in irq_show()
70 if (pdev->msi_enabled) in irq_show()
74 return sysfs_emit(buf, "%u\n", pdev->irq); in irq_show()
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/linux-6.12.1/drivers/media/pci/cobalt/
Dcobalt-driver.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Derived from cx18-driver.c
7 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
16 #include <media/v4l2-event.h>
17 #include <media/v4l2-ctrls.h>
19 #include "cobalt-driver.h"
20 #include "cobalt-irq.h"
21 #include "cobalt-i2c.h"
22 #include "cobalt-v4l2.h"
23 #include "cobalt-flash.h"
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