Searched full:mpcore (Results 1 – 25 of 33) sorted by relevance
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/marvell/ |
| D | armada-380-mpcore-soc-ctrl.txt | 1 Marvell Armada 38x CA9 MPcore SoC Controller
6 - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
9 datasheet for the CA9 MPcore SoC Control registers
11 mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | arm,scu.yaml | 13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
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| D | arm,realview.yaml | 15 earlier CPUs such as TrustZone and multicore (MPCore).
32 - description: ARM RealView Platform Baseboard for ARM 11 MPCore
34 multiprocessing with ARM11 using MPCore using symmetric
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| D | arm,vexpress-juno.yaml | 46 in MPCore configuration in a test chip on the core tile. See ARM
58 cores in a MPCore configuration in a test chip on the core tile. See
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
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| D | cpus.yaml | 51 On ARM 11 MPcore based systems this property is
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| /linux-6.12.1/arch/arm/boot/dts/arm/ |
| D | arm-realview-eb-a9mp.dts | 27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
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| D | arm-realview-eb-11mp.dts | 31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
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| D | arm-realview-eb-mp.dtsi | 28 * This is the common include file for all MPCore variants of the
30 * and Cortex-A9 MPCore.
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| D | arm-realview-eb-a9mp-bbrevd.dts | 27 model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore";
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| D | vexpress-v2p-ca5s.dts | 6 * Cortex-A5 MPCore (V2P-CA5s)
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| D | vexpress-v2p-ca15-tc1.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
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| D | vexpress-v2p-ca9.dts | 6 * Cortex-A9 MPCore (V2P-CA9)
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| /linux-6.12.1/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.yaml | 252 interrupts = <0 65 0x04>, /* mpcore syncpt */
253 <0 67 0x04>; /* mpcore general */
388 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
389 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
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| /linux-6.12.1/arch/arm/boot/dts/xen/ |
| D | xenvm-4.2.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
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| /linux-6.12.1/Documentation/arch/arm/keystone/ |
| D | overview.rst | 7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
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| /linux-6.12.1/arch/arm/boot/dts/broadcom/ |
| D | bcm5301x.dtsi | 12 mpcore-bus@19000000 {
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| D | bcm53573.dtsi | 35 mpcore@18310000 {
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| D | bcm-hr2.dtsi | 62 mpcore@19000000 {
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| D | bcm-ns.dtsi | 49 mpcore-bus@19000000 {
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| /linux-6.12.1/arch/arm/mach-mvebu/ |
| D | pmsu.c | 79 /* CA9 MPcore SoC Control registers */
443 "marvell,armada-380-mpcore-soc-ctrl"); in armada_38x_cpuidle_init()
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| /linux-6.12.1/arch/arm/boot/dts/marvell/ |
| D | armada-39x.dtsi | 303 mpcore-soc-ctrl@20d20 {
304 compatible = "marvell,armada-380-mpcore-soc-ctrl";
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| D | armada-38x.dtsi | 444 mpcore-soc-ctrl@20d20 {
445 compatible = "marvell,armada-380-mpcore-soc-ctrl";
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| /linux-6.12.1/arch/arm/mm/ |
| D | cache-v6.S | 32 * MPCore.
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| /linux-6.12.1/Documentation/devicetree/bindings/remoteproc/ |
| D | xlnx,zynqmp-r5fss.yaml | 42 The RPU MPCore can operate in split mode (Dual-processor performance), Safety
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| /linux-6.12.1/arch/arm/ |
| D | Kconfig | 552 It does not affect the MPCore. This option enables the ARM Ltd.
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
729 affecting Cortex-A9 MPCore with two or more processors (all
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