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/linux-6.12.1/Documentation/devicetree/bindings/display/
Dxylon,logicvc-display.yaml25 In version 3 of the controller, each layer has fixed memory offset and address
103 xylon,background-layer:
106 The last layer is used to display a black background (C_USE_BACKGROUND).
107 The layer must still be registered.
126 "^layer@[0-9]+$":
133 xylon,layer-depth:
135 description: Layer depth (C_LAYER_X_DATA_WIDTH).
137 xylon,layer-colorspace:
143 description: Layer colorspace (C_LAYER_X_TYPE).
145 xylon,layer-alpha-mode:
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/linux-6.12.1/drivers/gpu/drm/logicvc/
Dlogicvc_layer.c87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
111 ret = logicvc_layer_buffer_find_setup(logicvc, layer, new_state, in logicvc_plane_atomic_check()
123 layer->index != (logicvc->config.layers_count - 1) && in logicvc_plane_atomic_check()
140 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_update() local
149 u32 index = layer->index; in logicvc_plane_atomic_update()
152 /* Layer dimensions */ in logicvc_plane_atomic_update()
167 logicvc_layer_buffer_find_setup(logicvc, layer, new_state, in logicvc_plane_atomic_update()
170 /* Layer memory offsets */ in logicvc_plane_atomic_update()
180 /* Layer position */ in logicvc_plane_atomic_update()
185 /* Vertical position must be set last to sync layer register changes. */ in logicvc_plane_atomic_update()
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/linux-6.12.1/drivers/gpu/drm/xlnx/
Dzynqmp_disp.c69 * enum zynqmp_dpsub_layer_mode - Layer mode
95 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer
107 * struct zynqmp_disp_layer_info - Static layer information
119 * struct zynqmp_disp_layer - Display layer
120 * @id: Layer ID
122 * @info: Static layer information
200 /* List of video layer formats */
305 /* List of graphics layer formats */
370 /* List of live video layer formats */
415 static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer) in zynqmp_disp_layer_is_video() argument
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Dzynqmp_disp.h36 * enum zynqmp_dpsub_layer_id - Layer identifier
37 * @ZYNQMP_DPSUB_LAYER_VID: Video layer
38 * @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer
53 u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
55 u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer,
57 void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer);
58 void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer);
59 void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
61 void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer,
63 int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_qos.c79 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_leak_time() argument
83 value = spx5_rd(sparx5, HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_get_leak_time()
87 static void sparx5_lg_set_leak_time(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_set_leak_time() argument
91 HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_set_leak_time()
94 static u32 sparx5_lg_get_first(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_first() argument
98 value = spx5_rd(sparx5, HSCH_HSCH_LEAK_CFG(layer, group)); in sparx5_lg_get_first()
102 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_get_next() argument
112 static u32 sparx5_lg_get_last(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_last() argument
116 itr = sparx5_lg_get_first(sparx5, layer, group); in sparx5_lg_get_last()
119 next = sparx5_lg_get_next(sparx5, layer, group, itr); in sparx5_lg_get_last()
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/linux-6.12.1/Documentation/networking/caif/
Dlinux_caif.rst31 * CAIF Socket Layer and GPRS IP Interface.
33 * CAIF Link Layer, implemented as NET devices.
54 +--> ! HSI ! ! TTY ! ! USB ! <- Link Layer (Net Devices)
63 CAIF Core Protocol Layer
66 CAIF Core layer implements the CAIF protocol as defined by ST-Ericsson.
68 each layer described in the specification is implemented as a separate layer.
69 The architecture is inspired by the design patterns "Protocol Layer" and
78 - Layered architecture (a la Streams), each layer in the CAIF
80 - Clients must call configuration function to add PHY layer.
81 - Clients must implement CAIF layer to consume/produce
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/linux-6.12.1/drivers/gpu/drm/sun4i/
Dsun4i_layer.c69 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_disable() local
70 struct sun4i_backend *backend = layer->backend; in sun4i_backend_layer_atomic_disable()
72 sun4i_backend_layer_enable(backend, layer->id, false); in sun4i_backend_layer_atomic_disable()
89 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_update() local
90 struct sun4i_backend *backend = layer->backend; in sun4i_backend_layer_atomic_update()
93 sun4i_backend_cleanup_layer(backend, layer->id); in sun4i_backend_layer_atomic_update()
101 sun4i_backend_update_layer_frontend(backend, layer->id, in sun4i_backend_layer_atomic_update()
105 sun4i_backend_update_layer_formats(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
106 sun4i_backend_update_layer_buffer(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
109 sun4i_backend_update_layer_coord(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
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Dsun8i_ui_layer.c76 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", in sun8i_ui_layer_update_coord()
78 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); in sun8i_ui_layer_update_coord()
103 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", in sun8i_ui_layer_update_coord()
105 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_ui_layer_update_coord()
167 DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]); in sun8i_ui_layer_update_buffer()
186 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_ui_layer_atomic_check() local
202 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { in sun8i_ui_layer_atomic_check()
219 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_ui_layer_atomic_update() local
221 struct sun8i_mixer *mixer = layer->mixer; in sun8i_ui_layer_atomic_update()
226 sun8i_ui_layer_update_coord(mixer, layer->channel, in sun8i_ui_layer_atomic_update()
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Dsun8i_ui_layer.h17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
18 ((base) + 0x20 * (layer) + 0x0)
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
20 ((base) + 0x20 * (layer) + 0x4)
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
22 ((base) + 0x20 * (layer) + 0x8)
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
24 ((base) + 0x20 * (layer) + 0xc)
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
26 ((base) + 0x20 * (layer) + 0x10)
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Dsun8i_vi_layer.c102 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", in sun8i_vi_layer_update_coord()
105 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); in sun8i_vi_layer_update_coord()
183 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", in sun8i_vi_layer_update_coord()
185 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_vi_layer_update_coord()
296 DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n", in sun8i_vi_layer_update_buffer()
320 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_vi_layer_atomic_check() local
336 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { in sun8i_vi_layer_atomic_check()
352 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_vi_layer_atomic_update() local
354 struct sun8i_mixer *mixer = layer->mixer; in sun8i_vi_layer_atomic_update()
359 sun8i_vi_layer_update_coord(mixer, layer->channel, in sun8i_vi_layer_atomic_update()
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/linux-6.12.1/include/net/caif/
Dcaif_layer.h34 * enum caif_ctrlcmd - CAIF Stack Control Signaling sent in layer.ctrlcmd().
45 * @CAIF_CTRLCMD_INIT_RSP: Called initially when the layer below
53 * @_CAIF_CTRLCMD_PHYIF_FLOW_OFF_IND: CAIF Link layer temporarily cannot
55 * @_CAIF_CTRLCMD_PHYIF_FLOW_ON_IND: Called if CAIF Link layer is able
57 * @_CAIF_CTRLCMD_PHYIF_DOWN_IND: Called if CAIF Link layer is going
61 * They are used for signaling originating from the modem or CAIF Link Layer.
78 * to the CAIF Link Layer or modem.
86 * @_CAIF_MODEMCMD_PHYIF_USEFULL: Notify physical layer that it is in use
88 * @_CAIF_MODEMCMD_PHYIF_USELESS: Notify physical layer that it is
113 * struct cflayer - CAIF Stack layer.
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Dcaif_dev.h52 * @client_layer: User implementation of client layer. This layer
55 * @ifindex: Link layer interface index used for this connection.
60 * the struct cflayer. This layer represents the Client layer and holds
75 * @client_layer: Client layer to be disconnected.
83 * @adapt_layer: Client layer using CAIF Stack.
84 * @hold: Function provided by client layer increasing ref-count
85 * @put: Function provided by client layer decreasing ref-count
100 * @client_layer: Client layer to be removed.
102 * This function must be called from client layer in order to free memory.
109 * struct caif_enroll_dev - Enroll a net-device as a CAIF Link layer
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/linux-6.12.1/drivers/media/dvb-frontends/
Dmb86a20s.c377 unsigned layer) in mb86a20s_get_modulation() argument
381 [0] = 0x86, /* Layer A */ in mb86a20s_get_modulation()
382 [1] = 0x8a, /* Layer B */ in mb86a20s_get_modulation()
383 [2] = 0x8e, /* Layer C */ in mb86a20s_get_modulation()
386 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_modulation()
388 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_modulation()
409 unsigned layer) in mb86a20s_get_fec() argument
414 [0] = 0x87, /* Layer A */ in mb86a20s_get_fec()
415 [1] = 0x8b, /* Layer B */ in mb86a20s_get_fec()
416 [2] = 0x8f, /* Layer C */ in mb86a20s_get_fec()
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/linux-6.12.1/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_dc.h174 * Atmel HLCDC Layer registers layout structure
176 * Each HLCDC layer has its own register organization and a given register
179 * This structure stores common registers layout for a given layer and is
180 * used by HLCDC layer code to choose the appropriate register to write to
195 * @general_config: general layer config register
248 * Atmel HLCDC layer types
261 * This structure list all the formats supported by a given layer.
272 * Atmel HLCDC Layer description structure
274 * This structure describes the capabilities provided by a given layer.
276 * @name: layer name
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Datmel_hlcdc_plane.c281 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i, in atmel_hlcdc_plane_scaler_set_phicoeff()
289 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_hlcdc_plane_setup_scaler()
296 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_hlcdc_plane_setup_scaler()
328 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, in atmel_hlcdc_plane_setup_scaler()
338 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_xlcdc_plane_setup_scaler()
345 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_xlcdc_plane_setup_scaler()
356 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, in atmel_xlcdc_plane_setup_scaler()
362 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1, in atmel_xlcdc_plane_setup_scaler()
364 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3, in atmel_xlcdc_plane_setup_scaler()
377 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, in atmel_xlcdc_plane_setup_scaler()
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/linux-6.12.1/Documentation/gpu/
Dkomeda-kms.rst22 Layer section in Overview of D71 like display IPs
24 Layer is the first pipeline stage, which prepares the pixel data for the next
33 The usage of scaler is very flexible and can be connected to layer output
34 for layer scaling, or connected to compositor and scale the whole display
46 Writeback Layer (wb_layer)
48 Writeback layer does the opposite things of Layer, which connects to compiz
64 compared with Layer, like if Layer supports 4K input size, the scaler only can
66 introduces Layer Split, which splits the whole image to two half parts and feeds
73 Similar to Layer Split, but Splitter is used for writeback, which splits the
120 "Layer-0" -> "Scaler-0"
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/linux-6.12.1/fs/overlayfs/
Dexport.c36 * Before encoding a non-upper directory file handle from real layer N, we need
39 * "layer N connected" ancestor and verifying that all parents along the way are
40 * "layer N connectable". If an ancestor that is NOT "layer N connectable" is
41 * found, we need to copy up an ancestor, which is "layer N connectable", thus
42 * making that ancestor "layer N connected". For example:
44 * layer 1: /a
45 * layer 2: /a/b/c
47 * The overlay dentry /a is NOT "layer 2 connectable", because if dir /a is
49 * layer 1. The dir /a from layer 2 will never be indexed, so the algorithm (*)
54 * /a/b/c, which is "layer 2 connectable", on encode time. That ancestor is
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/linux-6.12.1/net/caif/
Dcaif_dev.c35 struct cflayer layer; member
161 caifd->layer.up-> in caif_flow_cb()
162 ctrlcmd(caifd->layer.up, in caif_flow_cb()
164 caifd->layer.id); in caif_flow_cb()
168 static int transmit(struct cflayer *layer, struct cfpkt *pkt) in transmit() argument
172 container_of(layer, struct caif_device_entry, layer); in transmit()
230 caifd->layer.up->ctrlcmd(caifd->layer.up, in transmit()
232 caifd->layer.id); in transmit()
259 if (!caifd || !caifd->layer.up || !caifd->layer.up->receive || in receive()
270 err = caifd->layer.up->receive(caifd->layer.up, pkt); in receive()
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Dcfserl.c22 struct cflayer layer; member
34 void cfserl_release(struct cflayer *layer) in cfserl_release() argument
36 kfree(layer); in cfserl_release()
44 caif_assert(offsetof(struct cfserl, layer) == 0); in cfserl_create()
45 this->layer.receive = cfserl_receive; in cfserl_create()
46 this->layer.transmit = cfserl_transmit; in cfserl_create()
47 this->layer.ctrlcmd = cfserl_ctrlcmd; in cfserl_create()
50 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "ser1"); in cfserl_create()
51 return &this->layer; in cfserl_create()
157 ret = layr->layer.up->receive(layr->layer.up, pkt); in cfserl_receive()
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/linux-6.12.1/drivers/net/ethernet/amazon/ena/
Dena_com.h378 * @ena_dev: ENA communication layer struct
389 * @ena_dev: ENA communication layer struct
397 * @ena_dev: ENA communication layer struct
402 * @ena_dev: ENA communication layer struct
407 * @ena_dev: ENA communication layer struct
419 * @ena_dev: ENA communication layer struct
428 * @ena_dev: ENA communication layer struct
437 * @ena_dev: ENA communication layer struct
448 * @ena_dev: ENA communication layer struct
454 * @ena_dev: ENA communication layer struct
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/linux-6.12.1/Documentation/driver-api/surface_aggregator/
Dinternal.rst63 Lower-level packet transport is implemented in the *packet transport layer
65 infrastructure of the kernel. As the name indicates, this layer deals with
70 Above this sits the *request transport layer (RTL)*. This layer is centered
76 The *controller* layer is building on top of this and essentially decides
81 ``RQID``). This layer basically provides a fundamental interface to the SAM
84 While the controller layer already provides an interface for other kernel
97 Packet Transport Layer
100 The packet transport layer is represented via |ssh_ptl| and is structured
107 managed by the packet transport layer, which is essentially the lowest layer
114 transport layer, as well as a reference to the buffer containing the data to
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/linux-6.12.1/block/
DKconfig3 # Block layer core configuration
6 bool "Enable the block layer" if EXPERT
11 Provide block layer support for the kernel.
13 Disable this option to remove the block layer support from the
22 they make use of various block layer definitions and facilities.
55 bool "Block layer SG support v4 helper lib"
64 bool "Block layer data integrity support"
69 stored/retrieved to help protect the data. The block layer
100 Block layer zoned block device support. This option enables
107 bool "Block layer bio throttling support"
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/linux-6.12.1/Documentation/hid/
Damd-sfh-hid.rst45 AMD HID Transport Layer
49 sensor data. The layer, which binds each device (AMD SFH HID driver) identifies the device type and
50 registers with the HID core. Transport layer attaches a constant "struct hid_ll_driver" object with
52 used by HID core to communicate with the device. AMD HID Transport layer implements the synchronous…
54 AMD HID Client Layer
56 This layer is responsible to implement HID requests and descriptors. As firmware is OS agnostic, HID
57 client layer fills the HID request structure and descriptors. HID client layer is complex as it is
58 interface between MP2 PCIe layer and HID. HID client layer initializes the MP2 PCIe layer and holds
59 the instance of MP2 layer. It identifies the number of sensors connected using MP2-PCIe layer. Based
61 enumeration of each sensor, client layer fills the HID Descriptor structure and HID input report
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/linux-6.12.1/Documentation/networking/
Dppp_generic.rst37 be linked to each ppp network interface unit. The generic layer is
46 functions used to communicate between the generic PPP layer and PPP
49 Each channel has to provide two functions to the generic PPP layer,
52 * start_xmit() is called by the generic layer when it has a frame to
56 later time when it can accept frames again, and the generic layer
66 The generic PPP layer provides seven functions to channels:
69 notify the PPP generic layer of its presence. For example, setting
89 generic layer to this channel. The channel should provide some way
97 Connecting a channel to the ppp generic layer is initiated from the
98 channel code, rather than from the generic layer. The channel is
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/linux-6.12.1/Documentation/userspace-api/media/
Dfrontend.h.rst.exceptions6 # Group layer A-C symbols together
7 replace define DTV_ISDBT_LAYERA_FEC dtv-isdbt-layer-fec
8 replace define DTV_ISDBT_LAYERB_FEC dtv-isdbt-layer-fec
9 replace define DTV_ISDBT_LAYERC_FEC dtv-isdbt-layer-fec
10 replace define DTV_ISDBT_LAYERA_MODULATION dtv-isdbt-layer-modulation
11 replace define DTV_ISDBT_LAYERB_MODULATION dtv-isdbt-layer-modulation
12 replace define DTV_ISDBT_LAYERC_MODULATION dtv-isdbt-layer-modulation
13 replace define DTV_ISDBT_LAYERA_SEGMENT_COUNT dtv-isdbt-layer-segment-count
14 replace define DTV_ISDBT_LAYERB_SEGMENT_COUNT dtv-isdbt-layer-segment-count
15 replace define DTV_ISDBT_LAYERC_SEGMENT_COUNT dtv-isdbt-layer-segment-count
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