Searched full:lane1 (Results 1 – 24 of 24) sorted by relevance
| /linux-6.12.1/Documentation/devicetree/bindings/display/bridge/ |
| D | analogix,anx7625.yaml | 72 analogix,lane1-swing:
77 an array of swing register setting for DP tx lane1 PHY.
78 DP TX lane1 swing register setting same with lane0
150 analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | phy-rockchip-usbdp.yaml | 60 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
62 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
63 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
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| D | airoha,en7581-pcie-phy.yaml | 23 - description: PCIE lane1 base address
25 - description: PCIE lane1 detection time base address
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| D | qcom,msm8996-qmp-pcie-phy.yaml | 88 - lane1
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| D | fsl,imx8qm-hsio.yaml | 55 | | Lane0| Lane1| Lane2|
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| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | mediatek-pcie-gen3.yaml | 86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
245 - const: phy-lane1
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| D | pci-armada8k.txt | 25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8186-corsola-steelix.dtsi | 64 analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
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| /linux-6.12.1/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 188 * lane1: PCIe/GbE0 PHY Configuration 1
209 * lane1: PCIe/GbE0 PHY Status 1
219 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
501 /* PCIE must be in Lane1 */ in mvebu_a3700_comphy_set_phy_selector()
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| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3588-friendlyelec-cm3588-nas.dts | 379 /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */
391 /* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */
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| D | rk3568.dtsi | 104 /* bifurcation; lane1 when using 1+1 */
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| /linux-6.12.1/drivers/gpu/drm/amd/display/include/ |
| D | grph_object_ctrl_defs.h | 243 uint8_t lane1:2; /* Mapping for lane 1 */ member
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| /linux-6.12.1/arch/arm64/boot/dts/marvell/ |
| D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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| D | armada-8040-puzzle-m801.dts | 521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
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| /linux-6.12.1/drivers/phy/rockchip/ |
| D | phy-rockchip-dphy-rx0.c | 212 /* HS RX Control of lane1 */ in rk_dphy_enable()
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| /linux-6.12.1/drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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| /linux-6.12.1/drivers/ufs/host/ |
| D | ufs-hisi.c | 62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
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| /linux-6.12.1/drivers/gpu/drm/msm/registers/display/ |
| D | dsi.xml | 99 <bitfield name="LANE1" pos="5" type="boolean"/>
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| /linux-6.12.1/drivers/pci/controller/ |
| D | pcie-mediatek-gen3.c | 1213 .id[1] = "phy-lane1",
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_training.c | 116 lt_result = "CR failed lane1"; in dp_log_training_result()
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| /linux-6.12.1/drivers/gpu/drm/bridge/analogix/ |
| D | anx7625.c | 1655 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane1-swing", in anx7625_get_swing_setting()
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| /linux-6.12.1/arch/arm64/boot/dts/qcom/ |
| D | msm8996.dtsi | 723 reset-names = "lane1";
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | atombios.h | 4113 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
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| /linux-6.12.1/drivers/gpu/drm/amd/include/ |
| D | atombios.h | 4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
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