| /linux-6.12.1/drivers/clk/ |
| D | clk-lochnagar.c | 147 struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw); in lochnagar_clk_prepare() local
148 struct lochnagar_clk_priv *priv = lclk->priv; in lochnagar_clk_prepare()
152 ret = regmap_update_bits(regmap, lclk->cfg_reg, in lochnagar_clk_prepare()
153 lclk->ena_mask, lclk->ena_mask); in lochnagar_clk_prepare()
156 lclk->name, ret); in lochnagar_clk_prepare()
163 struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw); in lochnagar_clk_unprepare() local
164 struct lochnagar_clk_priv *priv = lclk->priv; in lochnagar_clk_unprepare()
168 ret = regmap_update_bits(regmap, lclk->cfg_reg, lclk->ena_mask, 0); in lochnagar_clk_unprepare()
171 lclk->name, ret); in lochnagar_clk_unprepare()
176 struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw); in lochnagar_clk_set_parent() local
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/display/ |
| D | renesas,shmobile-lcdc.yaml | 37 - enum: [ media, lclk, hdmi, video ]
38 - enum: [ media, lclk, hdmi, video ]
39 - enum: [ media, lclk, hdmi, video ]
40 - enum: [ media, lclk, hdmi, video ]
116 clock-names = "fck", "media", "lclk", "video";
|
| /linux-6.12.1/drivers/gpu/drm/msm/dp/ |
| D | dp_debug.c | 29 u64 lclk = 0; in dp_debug_show() local
77 lclk = debug->link->link_params.rate * 1000; in dp_debug_show()
78 seq_printf(seq, "\t\tlclk = %lld\n", lclk); in dp_debug_show()
|
| /linux-6.12.1/drivers/usb/host/ |
| D | xhci-rcar.c | 38 #define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
64 /* LCLK Select */
78 /* LCLK Select */ in xhci_rcar_start_gen2()
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | aldebaran_ppt.h | 56 uint32_t lclk[ALDEBARAN_MAX_PCIE_CONF]; member
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | arcturus_ppt.h | 56 uint32_t lclk[MAX_PCIE_CONF]; member
|
| /linux-6.12.1/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.c | 67 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
2104 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, in check_horiz_timing_omap3() argument
2122 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); in check_horiz_timing_omap3()
2136 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); in check_horiz_timing_omap3()
2147 val = div_u64((u64)nonactive * lclk, pclk); in check_horiz_timing_omap3()
2249 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, in dispc_ovl_calc_scaling_24xx() argument
2295 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, in dispc_ovl_calc_scaling_34xx() argument
2326 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, in dispc_ovl_calc_scaling_34xx()
2361 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, in dispc_ovl_calc_scaling_34xx()
2380 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, in dispc_ovl_calc_scaling_44xx() argument
[all …]
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| D | sdi.c | 170 * LCLK and PCLK divisors are located in shadow registers, and we in sdi_display_enable()
|
| /linux-6.12.1/drivers/video/fbdev/ |
| D | pxafb.c | 990 * PixelClock = LCLK
994 * PCD = LCLK
999 * LCLK = LCD/Memory Clock
1005 * The function get_lclk_frequency_10khz returns LCLK in units of
1006 * 10khz. Calling the result of this function lclk gives us the
1009 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
1235 unsigned long lclk = clk_get_rate(fbi->clk); in setup_smart_timing() local
1245 LCCR1_BegLnDel(__smart_timing(t1, lclk)) | in setup_smart_timing()
1246 LCCR1_EndLnDel(__smart_timing(t2, lclk)) | in setup_smart_timing()
1247 LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); in setup_smart_timing()
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | aspeed,ast2500-pinctrl.yaml | 98 - LCLK
|
| D | nuvoton,npcm7xx-pinctrl.txt | 86 "GPIO162/SERIRQ", "GPIO163/LCLK/ESPICLK", "GPIO164/LAD0/ESPI_IO0",
|
| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | samsung,exynos4210-fimc.yaml | 37 Maximum FIMC local clock (LCLK) frequency.
|
| /linux-6.12.1/arch/x86/include/uapi/asm/ |
| D | amd_hsmp.h | 33 HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */
34 HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */
|
| /linux-6.12.1/drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.c | 103 unsigned long pclk, unsigned long lclk,
2139 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, in check_horiz_timing_omap3() argument
2159 lclk, pclk); in check_horiz_timing_omap3()
2173 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); in check_horiz_timing_omap3()
2184 val = div_u64((u64)nonactive * lclk, pclk); in check_horiz_timing_omap3()
2287 unsigned long pclk, unsigned long lclk, in dispc_ovl_calc_scaling_24xx() argument
2336 unsigned long pclk, unsigned long lclk, in dispc_ovl_calc_scaling_34xx() argument
2369 error = check_horiz_timing_omap3(pclk, lclk, vm, in dispc_ovl_calc_scaling_34xx()
2404 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width, in dispc_ovl_calc_scaling_34xx()
2424 unsigned long pclk, unsigned long lclk, in dispc_ovl_calc_scaling_44xx() argument
[all …]
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| D | sdi.c | 226 * LCLK and PCLK divisors are located in shadow registers, and we in sdi_bridge_enable()
|
| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | smu7.h | 43 #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | smu7.h | 43 #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels
|
| D | smu72.h | 111 #define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.h | 121 uint32_t lclk[MAX_PCIE_CONF]; member
|
| D | vega10_hwmgr.h | 143 uint32_t lclk[MAX_PCIE_CONF]; member
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| D | vega20_hwmgr.h | 174 uint32_t lclk[MAX_PCIE_CONF]; member
|
| /linux-6.12.1/drivers/gpu/drm/renesas/shmobile/ |
| D | shmob_drm_drv.c | 54 clkname = "lclk"; in shmob_drm_setup_clocks()
|
| /linux-6.12.1/arch/arm/boot/dts/nuvoton/ |
| D | nuvoton-npcm730-gsj-gpio.dtsi | 362 pins = "GPIO163/LCLK/ESPICLK";
|
| /linux-6.12.1/arch/arm/boot/dts/renesas/ |
| D | r8a7740.dtsi | 408 clock-names = "fck", "media", "lclk", "video";
432 clock-names = "fck", "media", "lclk", "video";
|
| /linux-6.12.1/drivers/gpu/drm/rockchip/ |
| D | cdn-dp-reg.c | 654 * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32 in cdn_dp_config_video()
655 * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes) in cdn_dp_config_video()
|