Searched full:hs200 (Results 1 – 25 of 255) sorted by relevance
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| /linux-6.12.1/Documentation/devicetree/bindings/mmc/ |
| D | cdns,sdhci.yaml | 95 HS200, HS400 and HS400_ES.
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
153 mmc-hs200-1_8v;
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| D | sprd,sdhci-r11.yaml | 101 mmc-hs200-1_8v;
108 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
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| D | mmc-controller.yaml | 205 mmc-hs200-1_2v:
208 eMMC HS200 mode (1.2V I/O) is supported.
210 mmc-hs200-1_8v:
213 eMMC HS200 mode (1.8V I/O) is supported.
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| D | sdhci-am654.yaml | 115 ti,otap-del-sel-hs200:
116 description: Output tap delay for eMMC HS200 timing
235 ti,otap-del-sel-hs200 = <0x5>;
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| D | mtk-sd.yaml | 101 mediatek,hs200-cmd-int-delay:
104 HS200 command internal delay setting.
336 mediatek,hs200-cmd-int-delay = <26>;
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| D | amlogic,meson-mx-sdhc.yaml | 18 It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
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| /linux-6.12.1/drivers/mmc/host/ |
| D | sdhci-acpi.c | 483 * read from the HS200 (SDR104) preset register. in amd_select_drive_strength()
499 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch in amd_select_drive_strength()
507 * card's timing to HS200 or HS400. The card will use the default driver in amd_select_drive_strength()
529 * HS->HS200->Perform Tuning->HS->HS400
532 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
534 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
536 * If we have previously performed tuning and switch back to HS200 or
632 * b) The HS200 and HS400 driver strengths don't match. in sdhci_acpi_emmc_amd_probe_slot()
635 * strength of B. As part of initializing HS400, HS200 tuning in sdhci_acpi_emmc_amd_probe_slot()
641 * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and in sdhci_acpi_emmc_amd_probe_slot()
[all …]
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| D | sdhci-xenon.c | 195 * Xenon defines different values for HS200 and HS400
286 * HS400/HS200/eMMC HS doesn't have Preset Value register. in xenon_set_ios()
287 * However, sdhci_set_ios will read HS400/HS200 Preset register. in xenon_set_ios()
288 * Disable Preset Value register for HS400/HS200. in xenon_set_ios()
429 /* Disable HS200 on Armada AP806 */ in xenon_probe_params()
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt7986a-bananapi-bpi-r3-emmc.dtso | 18 mmc-hs200-1_8v;
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| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3328-nanopi-r2s-plus.dts | 25 mmc-hs200-1_8v;
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| D | rk3328-nanopi-r2c-plus.dts | 26 mmc-hs200-1_8v;
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| D | rk3566-anbernic-rg-arc-d.dts | 52 mmc-hs200-1_8v;
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| D | rk3368-orion-r68-meta.dts | 171 mmc-hs200-1_2v;
172 mmc-hs200-1_8v;
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| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rk3288-tinker-s.dts | 22 mmc-hs200-1_8v;
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| /linux-6.12.1/arch/arm64/boot/dts/qcom/ |
| D | ipq5332-rdp474.dts | 28 mmc-hs200-1_8v;
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| D | ipq5332-rdp441.dts | 28 mmc-hs200-1_8v;
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| D | ipq9574-rdp433.dts | 22 mmc-hs200-1_8v;
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| D | ipq9574-rdp418.dts | 23 mmc-hs200-1_8v;
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| D | ipq5018-rdp432-c2.dts | 35 mmc-hs200-1_8v;
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| D | ipq5332-rdp442.dts | 42 mmc-hs200-1_8v;
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | tqmls10xxa.dtsi | 53 mmc-hs200-1_8v;
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| D | fsl-lx2162a-sr-som.dtsi | 27 mmc-hs200-1_8v;
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| /linux-6.12.1/arch/riscv/boot/dts/microchip/ |
| D | mpfs-polarberry.dts | 67 mmc-hs200-1_8v;
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| /linux-6.12.1/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 152 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
163 mmc-hs200-1_8v;
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| /linux-6.12.1/arch/arm64/boot/dts/allwinner/ |
| D | sun50i-h618-longan-module-3h.dtsi | 22 mmc-hs200-1_8v;
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