| /linux-6.12.1/include/kvm/ |
| D | arm_vgic.h | 40 VGIC_V2, /* Good ol' GICv2 */
68 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
146 u8 targets; /* GICv2 target VCPUs mask */
149 u8 source; /* GICv2 SGIs only */
150 u8 active_source; /* GICv2 SGIs only */
236 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
241 #define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */
245 /* Userspace can write to GICv2 IGROUPR */
256 /* either a GICv2 CPU interface */
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| /linux-6.12.1/Documentation/virt/kvm/devices/ |
| D | arm-vgic.rst | 17 guest GICv2 through this interface. For information on creating a guest GICv3
19 create both a GICv3 and GICv2 device on the same VM.
58 GICv2 specs. Getting or setting such a register has the same effect as
65 GICv2 is changed in a way directly observable by the guest or userspace.
92 defined in the GICv2 specs. Getting or setting such a register has the
96 fixed format for our implementation that fits with the model of a "GICv2
112 similar to GICv2's GICH_APR.
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| /linux-6.12.1/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-psci.dts | 4 * ARMv8 Foundation model DTS (GICv2+PSCI configuration)
8 #include "foundation-v8-gicv2.dtsi"
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| D | foundation-v8.dts | 5 * ARMv8 Foundation model DTS (GICv2 configuration)
9 #include "foundation-v8-gicv2.dtsi"
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| D | foundation-v8-gicv2.dtsi | 4 * ARMv8 Foundation model DTS (GICv2 configuration)
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| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | brcm,stb-pcie.yaml | 199 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
200 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
201 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
202 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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| /linux-6.12.1/arch/arm64/kvm/vgic/ |
| D | vgic-mmio-v2.c | 20 * Revision 1: Report GICv2 interrupts as group 0 instead of group 1
370 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_read_apr()
382 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr()
396 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_write_apr()
408 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
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| D | vgic-init.c | 33 * structures. Can be executed lazily for GICv2.
77 * which had no chance yet to check the availability of the GICv2 in kvm_vgic_create()
154 * initialization when using a virtual GICv2. in kvm_vgic_dist_init()
479 * is a GICv2. A GICv3 must be explicitly initialized by userspace using the
490 * for the legacy case of a GICv2. Any other type must in vgic_lazy_init()
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| D | vgic-v2.c | 194 /* The GICv2 LR only holds five bits of priority. */ in vgic_v2_populate_lr()
343 kvm_err("GICv2 not supported in protected mode\n"); in vgic_v2_probe()
382 kvm_err("Cannot register GICv2 KVM device\n"); in vgic_v2_probe()
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| D | vgic-mmio.c | 323 * GICv2 SGIs are terribly broken. We can't restore in __set_pending()
409 * More fun with GICv2 SGIs! If we're clearing one of them in __clear_pending()
466 * For GICv2 private interrupts we don't have to do anything because
570 * The GICv2 architecture indicates that the source CPUID for in vgic_mmio_change_active()
578 * for a GICv2 VM on some GIC implementations. Oh well. in vgic_mmio_change_active()
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| D | vgic-v3.c | 272 * If we are emulating a GICv3, we do it in an non-GICv2-compatible in vgic_v3_enable()
685 kvm_err("Cannot register GICv2 KVM device.\n"); in vgic_v3_probe()
698 kvm_info("disabling GICv2 emulation\n"); in vgic_v3_probe()
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| D | vgic-debug.c | 186 seq_printf(s, "vgic_model:\t%s\n", v3 ? "GICv3" : "GICv2"); in print_dist_state()
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-gic.c | 897 .name = "GICv2",
1299 * first page of a GICv2. in gic_check_eoimode()
1305 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode()
1314 * The first page was that of a GICv2, and in gic_check_eoimode()
1316 * to be a GICv2, and update the mapping. in gic_check_eoimode()
1318 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode()
1326 * We detected *two* initial GICv2 pages in a in gic_check_eoimode()
1327 * row. Could be a GICv2 aliased over two 64kB in gic_check_eoimode()
1335 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode()
1343 * Verify that we have the first 4kB of a GICv2 in gic_check_eoimode()
[all …]
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| /linux-6.12.1/tools/testing/selftests/kvm/aarch64/ |
| D | vgic_init.c | 136 * ARM_VGIC (GICv2 or GICv3) device gets created with an overlapping
137 * DIST/REDIST (or DIST/CPUIF for GICv2). Assumption is 4 vcpus are going to be
139 * and a DIST region is set @0x70000. The GICv2 case sets a CPUIF @0x0 and a
146 struct vgic_region_attr rdist; /* CPU interface in GICv2*/ in subtest_dist_rdist()
760 print_skip("No GICv2 nor GICv3 support"); in main()
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| /linux-6.12.1/include/linux/irqchip/ |
| D | arm-vgic-info.h | 14 /* Full GICv2 */
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| D | arm-gic-v3.h | 50 * Those registers are actually from GICv2, but the spec demands that they
580 /* These are for GICv2 emulation only */
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| /linux-6.12.1/arch/arm/boot/dts/broadcom/ |
| D | bcm2711.dtsi | 13 interrupt-parent = <&gicv2>;
56 gicv2: interrupt-controller@40041000 { label
566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
568 <0 0 0 2 &gicv2 GIC_SPI 144
570 <0 0 0 3 &gicv2 GIC_SPI 145
572 <0 0 0 4 &gicv2 GIC_SPI 146
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 101 For GICv2 with virtualization extensions, additional regions are
202 // GICv2
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| /linux-6.12.1/arch/arm64/boot/dts/broadcom/ |
| D | bcm2712.dtsi | 10 interrupt-parent = <&gicv2>;
259 gicv2: interrupt-controller@7fff9000 { label
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| /linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
| D | gpio-xgene-sb.txt | 12 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
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| /linux-6.12.1/arch/arm64/kvm/hyp/ |
| D | vgic-v3-sr.c | 264 * Group0 interrupt (as generated in GICv2 mode) to be in __vgic_v3_activate_traps()
422 * - [63] MMIO (GICv2) capable
430 * To check whether we have a MMIO-based (GICv2 compatible) in __vgic_v3_get_gic_config()
488 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen in __vgic_v3_restore_vmcr_aprs()
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| /linux-6.12.1/Documentation/translations/zh_TW/arch/arm64/ |
| D | booting.txt | 209 - 設備樹（DT）或 ACPI 表必須描述一個 GICv2 中斷控制器。
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| /linux-6.12.1/Documentation/translations/zh_CN/arch/arm64/ |
| D | booting.txt | 205 - 设备树（DT）或 ACPI 表必须描述一个 GICv2 中断控制器。
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| /linux-6.12.1/tools/testing/selftests/kvm/include/aarch64/ |
| D | gic_v3.h | 50 * Those registers are actually from GICv2, but the spec demands that they
580 /* These are for GICv2 emulation only */
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| /linux-6.12.1/Documentation/arch/arm64/ |
| D | memory.rst | 95 GICv2 gets mapped next to the HYP idmap page, as do vectors when
|