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18 Secondary GICs are cascaded into the upward interrupt controller and do not113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
144 * chips and call this to register their GICs.
48 * "performance interrupt". Luckily, on compliant GICs the polarity is in arm_pmu_acpi_register_irq()
700 MADT for GICs are expected to be in synchronization. The _UID of the Device769 - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT
651 * If we get one of these oddball non-GICs, taint the kernel, in kvm_vgic_hyp_init()
496 * because any nested/secondary GICs do not directly interface in gic_cpu_init()