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/linux-6.12.1/include/dt-bindings/clock/
Dqcom,gcc-sdx65.h106 #define GCC_PCIE_PHY_COM_BCR 13 macro
Dqcom,gcc-sdx55.h102 #define GCC_PCIE_PHY_COM_BCR 6 macro
Dqcom,qdu1000-gcc.h154 #define GCC_PCIE_PHY_COM_BCR 9 macro
Dqcom,sdx75-gcc.h183 #define GCC_PCIE_PHY_COM_BCR 16 macro
Dqcom,sm7150-gcc.h164 #define GCC_PCIE_PHY_COM_BCR 2 macro
Dqcom,sm4450-gcc.h174 #define GCC_PCIE_PHY_COM_BCR 10 macro
Dqcom,sm8550-gcc.h199 #define GCC_PCIE_PHY_COM_BCR 15 macro
Dqcom,gcc-sm8450.h215 #define GCC_PCIE_PHY_COM_BCR 16 macro
Dqcom,sm8650-gcc.h222 #define GCC_PCIE_PHY_COM_BCR 15 macro
Dqcom,gcc-sm8350.h229 #define GCC_PCIE_PHY_COM_BCR 15 macro
Dqcom,gcc-sm8250.h233 #define GCC_PCIE_PHY_COM_BCR 21 macro
Dqcom,gcc-msm8998.h287 #define GCC_PCIE_PHY_COM_BCR 81 macro
Dqcom,gcc-msm8996.h341 #define GCC_PCIE_PHY_COM_BCR 101 macro
Dqcom,gcc-sc8280xp.h440 #define GCC_PCIE_PHY_COM_BCR 38 macro
Dqcom,x1e80100-gcc.h443 #define GCC_PCIE_PHY_COM_BCR 46 macro
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dqcom,msm8996-qmp-pcie-phy.yaml141 <&gcc GCC_PCIE_PHY_COM_BCR>,
/linux-6.12.1/drivers/clk/qcom/
Dgcc-sdx65.c1529 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
Dgcc-sdx55.c1568 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
Dgcc-qdu1000.c2599 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
Dgcc-sdx75.c2879 [GCC_PCIE_PHY_COM_BCR] = { 0x88004 },
Dgcc-sm4450.c2774 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
Dgcc-sm8450.c3187 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
Dgcc-sm7150.c2913 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
Dgcc-msm8996.c3563 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
Dgcc-sm8550.c3261 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },

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