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/linux-6.12.1/include/dt-bindings/reset/
Dqcom,gcc-apq8084.h93 #define GCC_PCIE_1_PHY_BCR 84 macro
/linux-6.12.1/include/dt-bindings/clock/
Dqcom,sdx75-gcc.h173 #define GCC_PCIE_1_PHY_BCR 6 macro
Dqcom,gcc-sc7280.h212 #define GCC_PCIE_1_PHY_BCR 3 macro
Dqcom,sm8550-gcc.h195 #define GCC_PCIE_1_PHY_BCR 11 macro
Dqcom,gcc-sm8150.h220 #define GCC_PCIE_1_PHY_BCR 7 macro
Dqcom,gcc-sm8450.h211 #define GCC_PCIE_1_PHY_BCR 12 macro
Dqcom,gcc-sdm845.h230 #define GCC_PCIE_1_PHY_BCR 25 macro
Dqcom,sm8650-gcc.h218 #define GCC_PCIE_1_PHY_BCR 11 macro
Dqcom,gcc-sm8350.h226 #define GCC_PCIE_1_PHY_BCR 12 macro
Dqcom,gcc-sm8250.h224 #define GCC_PCIE_1_PHY_BCR 12 macro
Dqcom,gcc-sc8180x.h260 #define GCC_PCIE_1_PHY_BCR 7 macro
Dqcom,sa8775p-gcc.h277 #define GCC_PCIE_1_PHY_BCR 15 macro
Dqcom,gcc-msm8996.h322 #define GCC_PCIE_1_PHY_BCR 82 macro
Dqcom,gcc-sc8280xp.h411 #define GCC_PCIE_1_PHY_BCR 9 macro
Dqcom,x1e80100-gcc.h408 #define GCC_PCIE_1_PHY_BCR 11 macro
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dqcom,msm8996-qmp-pcie-phy.yaml168 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
/linux-6.12.1/drivers/clk/qcom/
Dgcc-sdx75.c2869 [GCC_PCIE_1_PHY_BCR] = { 0x56000 },
Dgcc-sm8450.c3183 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
Dgcc-msm8996.c3559 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
Dgcc-sc7280.c3399 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
Dgcc-sm8550.c3257 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
Dgcc-sm8250.c3548 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
Dgcc-sm8650.c3715 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
Dgcc-apq8084.c3590 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dmsm8996.dtsi722 resets = <&gcc GCC_PCIE_1_PHY_BCR>;

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