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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,gpucc.yaml51 - const: gcc_gpu_gpll0_div_clk_src
85 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
88 "gcc_gpu_gpll0_div_clk_src";
Dqcom,sm6115-gpucc.yaml52 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
Dqcom,qcm2290-gpucc.yaml69 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
Dqcom,sm6375-gpucc.yaml66 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
Dqcom,sm8450-gpucc.yaml63 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
/linux-6.12.1/drivers/clk/qcom/
Dgpucc-sdm845.c64 { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
Dgpucc-sc7280.c93 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
107 { .fw_name = "gcc_gpu_gpll0_div_clk_src", },
Dgpucc-sm8350.c116 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
130 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
/linux-6.12.1/include/dt-bindings/clock/
Dqcom,gcc-sc7180.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
Dqcom,sm7150-gcc.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 macro
Dqcom,gcc-qcm2290.h95 #define GCC_GPU_GPLL0_DIV_CLK_SRC 85 macro
Dqcom,sm4450-gcc.h44 #define GCC_GPU_GPLL0_DIV_CLK_SRC 34 macro
Dqcom,gcc-sm6115.h82 #define GCC_GPU_GPLL0_DIV_CLK_SRC 74 macro
Dqcom,gcc-sc7280.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
Dqcom,sm8550-gcc.h42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 31 macro
Dqcom,gcc-sm6125.h124 #define GCC_GPU_GPLL0_DIV_CLK_SRC 115 macro
Dqcom,sm6375-gcc.h109 #define GCC_GPU_GPLL0_DIV_CLK_SRC 98 macro
Dqcom,gcc-sm8150.h48 #define GCC_GPU_GPLL0_DIV_CLK_SRC 38 macro
Dqcom,gcc-sm8450.h56 #define GCC_GPU_GPLL0_DIV_CLK_SRC 44 macro
Dqcom,gcc-sdm845.h42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 32 macro
Dqcom,sm8650-gcc.h44 #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 macro
Dqcom,gcc-sm8350.h52 #define GCC_GPU_GPLL0_DIV_CLK_SRC 40 macro
Dqcom,gcc-sm8250.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
Dqcom,gcc-sc8180x.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
Dqcom,sa8775p-gcc.h72 #define GCC_GPU_GPLL0_DIV_CLK_SRC 61 macro

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