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/linux-6.12.1/Documentation/devicetree/bindings/fpga/
Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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Dxlnx,fpga-selectmap.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SelectMAP FPGA interface
10 - Charles Perry <charles.perry@savoirfairelinux.com>
22 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
27 - xlnx,fpga-xc7s-selectmap
28 - xlnx,fpga-xc7a-selectmap
29 - xlnx,fpga-xc7k-selectmap
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Dxlnx,fpga-slave-serial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
29 - xlnx,fpga-slave-serial
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Dmicrochip,mpf-spi-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Polarfire FPGA manager.
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
23 maxItems: 1
26 - compatible
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Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/lattice,sysconfig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
18 format into FPGA's SRAM configuration memory.
23 - lattice,sysconfig-ecp5
26 maxItems: 1
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/linux-6.12.1/Documentation/devicetree/bindings/board/
Dfsl,fpga-qixis.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA/CPLD
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - const: fsl,p1022ds-fpga
17 - const: fsl,fpga-ngpixis
18 - items:
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Dfsl,fpga-qixis-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA connected on I2C bus
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - enum:
17 - fsl,bsc9132qds-fpga
18 - const: fsl,fpga-qixis-i2c
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/linux-6.12.1/include/linux/fpga/
Dfpga-mgr.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FPGA Framework
5 * Copyright (C) 2013-2016 Altera Corporation
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
27 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
29 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
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/linux-6.12.1/drivers/hwmon/
Dintel-m10-bmc-hwmon.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
10 #include <linux/mfd/intel-m10-bmc.h>
40 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Die Temperature" },
50 { 0x128, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },
51 { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },
52 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
53 { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "12V Backplane Voltage" },
54 { 0x14c, 0x0, 0x0, 0x0, 0x0, 1, "1.2V Voltage" },
55 { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "12V AUX Voltage" },
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/linux-6.12.1/drivers/watchdog/
Dpika_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
29 #define DRV_NAME "PIKA-WDT"
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
72 * Bit 7, WTCHDG_EN: When set to 1, the watchdog timer is enabled. in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
77 * seconds. Valid ranges are 1 to 15 seconds. The value can in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
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/linux-6.12.1/Documentation/driver-api/fpga/
Dfpga-mgr.rst1 FPGA Manager
5 --------
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
24 --------------------------------
26 To add another FPGA manager, write a driver that implements a set of ops. The
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/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
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Dgef_sbc310.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00010000>; // FPGA
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
[all …]
Dge_imp3a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
11 /include/ "p2020si-pre.dtsi"
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
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/linux-6.12.1/drivers/fpga/
Dfpga-bridge.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Framework Driver
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 #include <linux/fpga/fpga-bridge.h>
23 * fpga_bridge_enable - Enable transactions on the bridge
25 * @bridge: FPGA bridge
31 dev_dbg(&bridge->dev, "enable\n"); in fpga_bridge_enable()
33 if (bridge->br_ops->enable_set) in fpga_bridge_enable()
34 return bridge->br_ops->enable_set(bridge, 1); in fpga_bridge_enable()
41 * fpga_bridge_disable - Disable transactions on the bridge
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Dsocfpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera SOCFPGA
5 * Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 "FPGA-1.5V",
99 "FPGA-1.1V",
100 "FPGA-2.5V",
120 [MSEL_PP16_FAST_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
121 [MSEL_PP16_FAST_AES_NODC] = { CFGWDTH_16 | CDRATIO_X2, 1 },
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Dts73xx-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
20 #define TS73XX_FPGA_CONFIG_REG 1
39 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
41 /* Reset the FPGA */ in ts73xx_fpga_write_init()
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
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/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dts-nbus.txt4 Systems FPGA on the TS-4600 SoM.
7 - compatible : "technologic,ts-nbus"
8 - #address-cells : must be 1
9 - #size-cells : must be 0
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
[all …]
/linux-6.12.1/Documentation/fpga/
Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/linux-6.12.1/drivers/fpga/tests/
Dfpga-region-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
61 * Fake FPGA manager that implements only the write op to count the number
72 struct bridge_stats *stats = bridge->priv; in op_enable_set()
74 if (!stats->enable && enable) in op_enable_set()
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/linux-6.12.1/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
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/linux-6.12.1/drivers/misc/
Dlattice-ecp3-config.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #define FIRMWARE_NAME "lattice-ecp3.bit"
19 * The JTAG ID's of the supported FPGA's. The ID is 32bit wide
25 /* FPGA commands */
41 #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */
57 .name = "Lattice ECP3-17",
61 .name = "Lattice ECP3-35",
78 dev_err(&spi->dev, "Cannot load firmware, aborting\n"); in firmware_load()
82 if (fw->size == 0) { in firmware_load()
83 dev_err(&spi->dev, "Error: Firmware size is 0!\n"); in firmware_load()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Darm,versatile-fpga-irq.txt1 * ARM Versatile FPGA interrupt controller
3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
9 - compatible: "arm,versatile-fpga-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
12 as the FPGA IRQ controller has no configuration options for interrupt
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
22 The "oxsemi,ox810se-rps-irq" compatible is deprecated.
[all …]
/linux-6.12.1/arch/powerpc/platforms/44x/
Dwarp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2008-2009 PIKA Technologies
58 void __iomem *fpga; in warp_post_info() local
62 np = of_find_compatible_node(NULL, NULL, "pika,fpga-sd"); in warp_post_info()
64 return -ENOENT; in warp_post_info()
66 fpga = of_iomap(np, 0); in warp_post_info()
68 if (fpga == NULL) in warp_post_info()
69 return -ENOENT; in warp_post_info()
71 post1 = in_be32(fpga + 0x40); in warp_post_info()
72 post2 = in_be32(fpga + 0x44); in warp_post_info()
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/linux-6.12.1/arch/sh/boards/mach-sdk7786/
Dsram.c1 // SPDX-License-Identifier: GPL-2.0
3 * SDK7786 FPGA SRAM Support.
14 #include <mach/fpga.h>
26 /* Enable FPGA SRAM */ in fpga_sram_init()
36 pr_err("FPGA memory unmapped.\n"); in fpga_sram_init()
37 return -ENXIO; in fpga_sram_init()
44 phys = (area << 26) + SZ_64M - SZ_4K; in fpga_sram_init()
47 * The FPGA SRAM resides in translatable physical space, so set in fpga_sram_init()
52 pr_err("Failed remapping FPGA memory.\n"); in fpga_sram_init()
53 return -ENXIO; in fpga_sram_init()
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