Searched full:exynosauto (Results 1 – 8 of 8) sorted by relevance
144 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.145 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.146 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.175 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.176 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.177 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
7 title: Samsung ExynosAuto v920 SoC clock controller16 ExynosAuto v920 clock controller is comprised of several CMU units, generating
3 * UFS PHY driver data for Samsung EXYNOSAUTO v9 SoC
15 model = "Samsung ExynosAuto v9 SADK board";
3 * Samsung's ExynosAuto v9 SoC device tree source
6 * Device Tree binding constants for ExynosAuto v920 clock controller.
6 * Common Clock Framework support for ExynosAuto v920 SoC.
6 * Common Clock Framework support for ExynosAuto V9 SoC.