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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_dpia_bw.c212 * HR BW = Estimated(dpia_primary) + Allocated(dpia_secondary) in get_host_router_total_dp_tunnel_bw()
213 * otherwise HR BW = Estimated(bw alloc enabled dpia) in get_host_router_total_dp_tunnel_bw()
259 DC_LOG_ERROR("%s: Request bw greater than estimated bw for link(%d)\n", in set_usb4_req_bw_req()
346 * During DP tunnel creation, CM preallocates BW and reduces estimated BW of other in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
348 * to make the CM to release preallocation and update estimated BW correctly for in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
362 int estimated = 0; in dpia_handle_bw_alloc_response() local
375 estimated = bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity); in dpia_handle_bw_alloc_response()
380 __func__, link->dpia_bw_alloc_config.estimated_bw, estimated); in dpia_handle_bw_alloc_response()
382 /* Update the new Estimated BW value updated by CM */ in dpia_handle_bw_alloc_response()
383 link->dpia_bw_alloc_config.estimated_bw = estimated; in dpia_handle_bw_alloc_response()
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/linux-6.12.1/tools/perf/pmu-events/arch/s390/cf_z14/
Dtransaction.json53 "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
58 "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
63 "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
68 "BriefDescription": "Estimated Cycles per TLB Miss",
/linux-6.12.1/tools/perf/pmu-events/arch/s390/cf_z15/
Dtransaction.json53 "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
58 "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
63 "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
68 "BriefDescription": "Estimated Cycles per TLB Miss",
/linux-6.12.1/tools/perf/pmu-events/arch/s390/cf_z13/
Dtransaction.json53 "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
58 "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
63 "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
68 "BriefDescription": "Estimated Cycles per TLB Miss",
/linux-6.12.1/tools/perf/pmu-events/arch/s390/cf_z16/
Dtransaction.json53 "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
58 "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
63 "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
68 "BriefDescription": "Estimated Cycles per TLB Miss",
/linux-6.12.1/tools/power/cpupower/bench/
Dbenchmark.c36 unsigned int estimated = GAUGECOUNT; in calculate_timespace() local
45 ROUNDS(estimated); in calculate_timespace()
53 rounds = (unsigned int)(load * estimated / timed); in calculate_timespace()
60 estimated = rounds; in calculate_timespace()
65 return estimated; in calculate_timespace()
/linux-6.12.1/net/ipv4/
Dtcp_bbr.c4 * rate (throughput) estimated from ACKs. In a nutshell:
44 * we estimated that we reached the full bw of the pipe then we enter PROBE_BW;
84 BBR_PROBE_BW, /* discover, share bw: pace around estimated bw */
141 /* Pace at ~1% below estimated bw, on average, to reduce queue at bottleneck.
144 * lower than the estimated bandwidth. This is an important aspect of the
222 /* Return the estimated bandwidth of the path, in pkts/uS << BW_SCALE. */
351 /* Calculate bdp based on min RTT and the estimated bottleneck bandwidth:
412 /* Find inflight based on min RTT and the estimated bottleneck bandwidth. */
476 * recovery started (capped by the target cwnd based on estimated BDP).
564 /* The pacing_gain of 1.0 paces at the estimated bw to try to fully in bbr_is_next_cycle_phase()
[all …]
Dtcp_hybla.c122 * Inrement<<7 is estimated by doing: in hybla_cong_avoid()
137 * as long as increment is estimated as (rho<<7)/window in hybla_cong_avoid()
Dtcp_rate.c167 * Note that rate may still be over-estimated when a spuriously in tcp_rate_gen()
169 * is under-estimated (up to an RTT). However continuously in tcp_rate_gen()
/linux-6.12.1/drivers/md/
Ddm-ps-historical-service-time.c13 * will never have the best estimated service time, or if the entire
358 * Compare the estimated service time of 2 paths, pi1 and pi2,
378 /* Check here if estimated latency for two paths are too similar. in hst_compare()
400 /* Compare estimated service time. If outstanding is the same, we in hst_compare()
511 * finished any requests within the fresh period, the estimated in hst_end_io()
Ddm-ps-service-time.c201 * Compare the estimated service time of 2 paths, pi1 and pi2,
210 * Basically, the service time is estimated by:
/linux-6.12.1/Documentation/admin-guide/device-mapper/
Ddm-service-time.rst6 which selects a path with the shortest estimated service time for
9 The service time for each path is estimated by dividing the total size
/linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen5/
Drecommended.json307 "BriefDescription": "Estimated memory read bandwidth.",
315 "BriefDescription": "Estimated memory write bandwidth.",
323 "BriefDescription": "Estimated combined memory bandwidth.",
/linux-6.12.1/include/uapi/linux/
Dtimex.h70 __kernel_long_t esterror;/* estimated error (usec) */
108 long long esterror;/* estimated error (usec) */
142 #define ADJ_ESTERROR 0x0008 /* estimated time error */
/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-cfq-target-latency7 It contains an estimated latency time for the cfq. cfq will
/linux-6.12.1/Documentation/admin-guide/pm/
Dcpufreq.rst452 estimated for all of them and the greatest result is taken as the load estimate
464 It generally selects CPU frequencies proportional to the estimated load, so that
490 If the estimated CPU load is above this value (in percent), the governor
492 Otherwise, the selected frequency will be proportional to the estimated
520 value is exceeded by the estimated CPU load) or sensitivity threshold
566 (configurable) threshold has been exceeded by the estimated CPU load.
585 If the estimated CPU load is greater than this value, the frequency will
/linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen4/
Drecommended.json367 "BriefDescription": "Estimated memory read bandwidth.",
375 "BriefDescription": "Estimated memory write bandwidth.",
383 "BriefDescription": "Estimated combined memory bandwidth.",
/linux-6.12.1/net/batman-adv/
Dmulticast_forw.c87 * @count: the (estimated) number of originators the multicast packet needs to
428 * @count: the estimated number of originators the multicast packet needs to
435 * initially estimated amount of destinations versus the amount of destinations
440 * If the initially estimated number was even, so padding was initially added,
442 * If the initially estimated number was odd, so no padding was initially added,
459 * estimated even number of destinations, but turned out to be odd in batadv_mcast_forw_push_adjust_padding()
465 * estimated odd number of destinations, but turned out to be even in batadv_mcast_forw_push_adjust_padding()
/linux-6.12.1/Documentation/devicetree/bindings/rng/
Dtimeriomem_rng.yaml24 Estimated number of bits of true entropy per 1024 bits read from the rng.
/linux-6.12.1/include/linux/
Dbacking-dev-defs.h123 unsigned long write_bandwidth; /* the estimated write bandwidth */
129 * @dirty_ratelimit tracks the estimated @balanced_dirty_ratelimit
/linux-6.12.1/drivers/net/wireless/broadcom/b43/
Dtables_nphy.h156 #define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */
162 #define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
/linux-6.12.1/sound/pci/emu10k1/
Dp17v.h133 #define P17V_SRP_P17V_ESR 0x8B /* SRP_P17V estimated sample rate and rate lock */
134 #define P17V_SRP_REC_ESR 0x8C /* SRP_REC estimated sample rate and rate lock */
/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dcadence-nand-controller.txt17 - cdns,board-delay-ps : Estimated Board delay. The value includes the total
/linux-6.12.1/drivers/net/wireless/virtual/
Dmac80211_hwsim.h123 * @HWSIM_ATTR_RX_RATE: estimated rx rate index for this frame at user
125 * @HWSIM_ATTR_SIGNAL: estimated RX signal for this frame at user
/linux-6.12.1/kernel/sched/
Dfeatures.h111 * UtilEstimation. Use estimated CPU utilization.

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