| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-exynos-audss.c | 25 * access to audss registers. Typically a child of EPLL.
29 static struct clk *epll; variable
142 epll = ERR_PTR(-ENODEV); in exynos_audss_clk_probe()
162 epll = pll_in; in exynos_audss_clk_probe()
164 ret = clk_prepare_enable(epll); in exynos_audss_clk_probe()
167 "failed to prepare the epll clock\n"); in exynos_audss_clk_probe()
264 if (!IS_ERR(epll)) in exynos_audss_clk_probe()
265 clk_disable_unprepare(epll); in exynos_audss_clk_probe()
277 if (!IS_ERR(epll)) in exynos_audss_clk_remove()
278 clk_disable_unprepare(epll); in exynos_audss_clk_remove()
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| D | clk-exynos5410.c | 64 apll, cpll, epll, mpll, enumerator
247 [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
275 exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl; in exynos5410_clk_init()
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| D | clk-s5pv210.c | 70 epll, enumerator
720 [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
732 [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
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| D | clk-exynos4.c | 150 apll, mpll, epll, vpll, enumerator
1156 [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1167 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1301 exynos4210_plls[epll].rate_table = in exynos4_clk_init()
1315 exynos4x12_plls[epll].rate_table = in exynos4_clk_init()
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| D | clk-exynos5250.c | 108 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
746 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
814 exynos5250_plls[epll].rate_table = epll_24mhz_tbl; in exynos5250_clk_init()
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| D | clk-exynos5420.c | 153 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1471 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1602 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; in exynos5x_clk_init()
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| D | clk-exynos3250.c | 695 /* EPLL */
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | nuvoton,ma35d1-clk.h | 23 #define EPLL 12 macro
25 /* EPLL divider */
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| /linux-6.12.1/sound/soc/samsung/ |
| D | arndale.c | 73 * We add 1 to the frequency value to ensure proper EPLL setting in arndale_wm1811_hw_params()
75 * samsung/clk-exynos5250.c for list of available EPLL rates). in arndale_wm1811_hw_params()
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| D | odroid.c | 90 * frequency values due to the EPLL output frequency not being exact in odroid_card_be_hw_params()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | nuvoton,ma35d1-clk.yaml | 37 EPLL, and VPLL in sequential.
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| /linux-6.12.1/drivers/clk/nuvoton/ |
| D | clk-ma35d1.c | 104 { .fw_name = "epll", },
508 hws[EPLL] = ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll", in ma35d1_clocks_probe()
513 hws[EPLL_DIV2] = ma35d1_clk_fixed_factor(dev, "epll_div2", "epll", 1, 2); in ma35d1_clocks_probe()
514 hws[EPLL_DIV4] = ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4); in ma35d1_clocks_probe()
515 hws[EPLL_DIV8] = ma35d1_clk_fixed_factor(dev, "epll_div8", "epll", 1, 8); in ma35d1_clocks_probe()
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| D | clk-ma35d1-pll.c | 237 case EPLL: in ma35d1_clk_pll_recalc_rate()
269 case EPLL: in ma35d1_clk_pll_round_rate()
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| /linux-6.12.1/drivers/clk/ |
| D | clk-ast2600.c | 116 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
211 /* For hpll/dpll/epll/mpll */
475 "epll",
663 hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0, in aspeed_g6_clk_probe()
770 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); in aspeed_g6_cc()
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| /linux-6.12.1/arch/arm64/boot/dts/nuvoton/ |
| D | ma35d1-som-256m.dts | 44 <&clk EPLL>,
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| D | ma35d1-iot-512m.dts | 44 <&clk EPLL>,
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| /linux-6.12.1/drivers/clk/ingenic/ |
| D | jz4780-cgu.c | 305 "epll", CGU_CLK_PLL,
307 .pll = DEF_PLL(EPLL),
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| D | x1830-cgu.c | 159 "epll", CGU_CLK_PLL,
|