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/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt48 clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2
51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
101 spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
Dmediatek,mt7620-pinctrl.yaml38 enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand,
56 const: ephy
60 enum: [ephy]
69 enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi,
/linux-6.12.1/drivers/pinctrl/
Dpinctrl-xway.c117 MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
118 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
119 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
204 GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
205 GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
206 GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
215 static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
216 "ephy led2"};
234 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
887 MFP_XWAY(GPIO0, GPIO, EXIN, EPHY, NONE),
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/leds/
Dleds-bcm6328.yaml121 /* BCM6328 with 4 EPHY LEDs */
263 /* BCM6362 with 1 LED for each EPHY */
336 ephy@4 {
351 /* BCM6362 with EPHY LEDs swapped */
/linux-6.12.1/arch/mips/bcm63xx/
Dclk.c428 CLKDEV_INIT(NULL, "ephy", &clk_ephy),
458 CLKDEV_INIT(NULL, "ephy", &clk_ephy),
472 CLKDEV_INIT(NULL, "ephy", &clk_ephy),
486 CLKDEV_INIT(NULL, "ephy", &clk_ephy),
502 CLKDEV_INIT(NULL, "ephy", &clk_ephy),
/linux-6.12.1/drivers/net/ethernet/broadcom/
Db44.h11 #define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */
12 #define DEVCTRL_EPR 0x00008000 /* EPHY Reset */
60 #define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
61 #define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected */
62 #define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */
/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mt7620.c64 static struct mtmips_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
108 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sun8i.c62 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
64 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
260 /* H3 specific bits for EPHY */
835 /* Make sure the EPHY is properly reseted, as U-Boot may leave in sun8i_dwmac_power_internal_phy()
838 * This assumes the driver has exclusive access to the EPHY reset. in sun8i_dwmac_power_internal_phy()
956 /* Force EPHY xtal frequency to 24MHz. */ in sun8i_dwmac_set_syscon()
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun8i-a83t-cubietruck-plus.dts361 regulator-name = "ephy-io";
373 regulator-name = "ephy";
Dsun8i-s3-pinecube.dts169 regulator-name = "vdd-sys-cpu-ephy";
Dsun8i-v3s-anbernic-rg-nano.dts183 /* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */
Dsun8i-a83t-allwinner-h8homlet-v2.dts238 regulator-name = "vcc-ephy";
/linux-6.12.1/drivers/clk/bcm/
Dclk-bcm63xx-gate.c79 .name = "ephy",
280 .name = "ephy",
/linux-6.12.1/drivers/net/phy/
Drockchip.c177 .name = "Rockchip integrated EPHY",
Dbcm7xxx.c19 /* EPHY only register definitions */
299 /* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt7629-rfb.dts161 ephy_leds_pins: ephy-leds-pins {
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dallwinner,sun8i-a83t-emac.yaml125 EPHY LEDs are active low.
/linux-6.12.1/drivers/scsi/libsas/
Dsas_expander.c874 struct ex_phy *ephy = &parent->ex_dev.ex_phy[i]; in sas_ex_join_wide_port() local
876 if (ephy == phy) in sas_ex_join_wide_port()
879 if (!memcmp(phy->attached_sas_addr, ephy->attached_sas_addr, in sas_ex_join_wide_port()
880 SAS_ADDR_SIZE) && ephy->port) { in sas_ex_join_wide_port()
881 sas_port_add_ex_phy(ephy->port, phy); in sas_ex_join_wide_port()
/linux-6.12.1/drivers/pmdomain/bcm/
Dbcm63xx-power.c243 .name = "ephy",
/linux-6.12.1/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-orangepi-3.dts213 regulator-name = "vcc33-audio-tv-ephy-mac";
/linux-6.12.1/arch/mips/lantiq/xway/
Dsysctrl.c28 /* ephy configuration register */
536 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY); in ltq_soc_init()
/linux-6.12.1/arch/mips/boot/dts/brcm/
Dbcm7420.dtsi257 compatible = "brcm,65nm-ephy",
Dbcm7358.dtsi285 compatible = "brcm,40nm-ephy",
/linux-6.12.1/drivers/net/mdio/
Dmdio-mux-meson-g12a.c162 /* Initialize ephy control */ in g12a_enable_internal_mdio()
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3328-rock-pi-e.dts372 ephy {

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