Searched full:emc_sel_dpd_ctrl (Results 1 – 5 of 5) sorted by relevance
| /linux-6.12.1/drivers/memory/tegra/ |
| D | tegra210-emc-cc-r21021.c | 363 u32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock() local
420 emc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock()
421 emc_sel_dpd_ctrl &= ~(EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN | in tegra210_emc_r21021_set_clock()
473 emc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
496 emc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
1455 emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
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| D | tegra124-emc.c | 200 #define EMC_SEL_DPD_CTRL 0x3d8 macro
464 u32 emc_sel_dpd_ctrl; member
634 val = readl(emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
637 writel(val, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
968 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") in load_one_timing_from_dt()
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| D | tegra210-emc.h | 187 #define EMC_SEL_DPD_CTRL 0x3d8 macro
867 u32 emc_sel_dpd_ctrl; member
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| D | tegra30-emc.c | 146 #define EMC_SEL_DPD_CTRL 0x3d8 macro
666 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); in emc_prepare_timing_change()
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 144 value of the EMC_SEL_DPD_CTRL register for this set of timings
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