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/linux-6.12.1/drivers/memory/tegra/
Dtegra210-emc.h117 #define EMC_MRW4 0x13c macro
853 u32 emc_mrw4; member
Dtegra124-emc.c122 #define EMC_MRW4 0x13c macro
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
Dtegra210-emc-cc-r21021.c1254 ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0); in tegra210_emc_r21021_set_clock()
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml129 value of the EMC_MRW4 register for this set of timings