Searched full:emc_ctt_term_ctrl (Results 1 – 7 of 7) sorted by relevance
409 0x00000802 /* EMC_CTT_TERM_CTRL */513 0x00000802 /* EMC_CTT_TERM_CTRL */617 0x00000802 /* EMC_CTT_TERM_CTRL */721 0x00000802 /* EMC_CTT_TERM_CTRL */823 0x00000802 /* EMC_CTT_TERM_CTRL */926 0x00000802 /* EMC_CTT_TERM_CTRL */1034 0x00000802 /* EMC_CTT_TERM_CTRL */1138 0x00000802 /* EMC_CTT_TERM_CTRL */1242 0x00000802 /* EMC_CTT_TERM_CTRL */1346 0x00000802 /* EMC_CTT_TERM_CTRL */[all …]
104 0x00000802 /* EMC_CTT_TERM_CTRL */208 0x00000802 /* EMC_CTT_TERM_CTRL */311 0x00000802 /* EMC_CTT_TERM_CTRL */
2747 0x00000802 /* EMC_CTT_TERM_CTRL */2849 0x00000802 /* EMC_CTT_TERM_CTRL */2951 0x00000802 /* EMC_CTT_TERM_CTRL */3053 0x00000802 /* EMC_CTT_TERM_CTRL */3153 0x00000802 /* EMC_CTT_TERM_CTRL */3254 0x00000802 /* EMC_CTT_TERM_CTRL */3360 0x00000802 /* EMC_CTT_TERM_CTRL */3462 0x00000802 /* EMC_CTT_TERM_CTRL */3564 0x00000802 /* EMC_CTT_TERM_CTRL */3666 0x00000802 /* EMC_CTT_TERM_CTRL */[all …]
146 #define EMC_CTT_TERM_CTRL 0x2dc macro458 u32 emc_ctt_term_ctrl; member688 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { in tegra_emc_prepare_timing_change()690 writel(timing->emc_ctt_term_ctrl, in tegra_emc_prepare_timing_change()691 emc->regs + EMC_CTT_TERM_CTRL); in tegra_emc_prepare_timing_change()837 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) in tegra_emc_complete_timing_change()962 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") in load_one_timing_from_dt()
103 #define EMC_CTT_TERM_CTRL 0x2dc macro318 [79] = EMC_CTT_TERM_CTRL,
197 - description: EMC_CTT_TERM_CTRL342 0x00000802 /* EMC_CTT_TERM_CTRL */
114 value of the EMC_CTT_TERM_CTRL register for this set of timings