| /linux-6.12.1/Documentation/devicetree/bindings/regulator/ |
| D | dlg,da9121.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adam Ward <Adam.Ward.opensource@diasemi.com>
13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
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| /linux-6.12.1/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
35 * Channel
37 A memory controller channel, responsible to communicate with a group of
38 DIMMs. Each channel has its own independent control (command) and data
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
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| /linux-6.12.1/Documentation/devicetree/bindings/power/supply/ |
| D | maxim,max17040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
18 - maxim,max17040
19 - maxim,max17041
20 - maxim,max17043
21 - maxim,max17044
22 - maxim,max17048
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| /linux-6.12.1/Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
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| /linux-6.12.1/Documentation/sound/cards/ |
| D | hdspm.rst | 2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
32 (Note: Choosing the 56channel mode for transmission or as
34 all 64 channels are available for the mixer, so channel count
37 * Double Speed -- 1..32 channels
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| /linux-6.12.1/include/sound/ |
| D | ak4114.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
20 #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
21 #define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */
22 #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
23 #define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */
24 #define AK4114_REG_TXCSB0 0x0d /* TX channel status byte 0 */
25 #define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */
26 #define AK4114_REG_TXCSB2 0x0f /* TX channel status byte 2 */
27 #define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */
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| D | ac97_codec.h | 1 /* SPDX-License-Identifier: GPL-2.0+
24 /* specific - SigmaTel */
33 #define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */
37 /* specific - Analog Devices */
47 /* specific - Cirrus Logic */
56 /* specific - Conexant */
64 /* specific - ALC */
81 #define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */
106 /* specific - Yamaha YMF7x3 */
110 /* specific - C-Media */
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| /linux-6.12.1/drivers/video/fbdev/ |
| D | pxa3xx-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
21 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
22 #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
23 #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
24 #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
25 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
26 #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
49 #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
50 #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
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| /linux-6.12.1/drivers/net/wireless/ti/wl1251/ |
| D | rx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 1998-2007 Texas Instruments Incorporated
19 * The Rx path uses a double buffer and an rx_contro structure, each located
27 * 2) The host reads the received packet from one of the double buffers.
32 #define WL1251_RX_MAX_RSSI -30
33 #define WL1251_RX_MIN_RSSI -95
36 #define WL1251_RX_ALIGN(len) (((len) + WL1251_RX_ALIGN_TO - 1) & \
37 ~(WL1251_RX_ALIGN_TO - 1))
67 * 0 - 802.11
68 * 1 - 802.3
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| /linux-6.12.1/drivers/media/rc/keymaps/ |
| D | rc-powercolor-real-angel.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // powercolor-real-angel.h - Keytable for powercolor_real_angel Remote Controller
4 // keymap imported from ir-keymaps.c
8 #include <media/rc-map.h>
29 { 0x0a, KEY_DIGITS }, /* single, double, triple digit */
30 { 0x29, KEY_PREVIOUS }, /* previous channel */
35 { 0x20, KEY_CHANNELUP }, /* channel up */
36 { 0x21, KEY_CHANNELDOWN }, /* channel down */
|
| D | rc-mygica-utv3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* rc-mygica-utv3.c - Keytable for the MyGica UTV3 Analog USB2.0 TV Box
7 #include <media/rc-map.h>
27 { 0x0a, KEY_DIGITS }, /* Single/double/triple digit */
30 { 0x29, KEY_LAST }, /* Recall (return to previous channel) */
|
| /linux-6.12.1/Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7923.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD7923 and similars with 4 and 8 Channel ADCs.
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices AD7904, AD7914, AD7923, AD7924 4 Channel ADCs, and AD7908,
17 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7923.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7904_7914_7924.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7908_7918_7928.pdf
24 - enum:
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | umc_v6_7.h | 34 #define UMC_V6_7_CE_CNT_INIT (UMC_V6_7_CE_CNT_MAX - UMC_V6_7_CE_INT_THRESHOLD)
38 /* number of umc channel instance with memory map register access */
42 /* total channel instances in one umc block */
46 /* R14 bit shift should be considered, double the number */
54 /* UMC regiser per channel offset */
61 (((pa) >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
62 (((pa) >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
63 (((pa) >> 34) & 0x1ULL & adev->df.hash_status.hash_1g))
|
| D | umc_v12_0.h | 32 /* UMC register per channel offset */
43 #define UMC_V12_0_CE_CNT_INIT (UMC_V12_0_CE_CNT_MAX - UMC_V12_0_CE_INT_THRESHOLD)
45 /* number of umc channel instance with memory map register access */
50 /* Total channel instances for all available umc nodes */
52 (UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
56 /* R13 bit shift should be considered, double the number */
|
| /linux-6.12.1/drivers/staging/sm750fb/ |
| D | sm750.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
18 sm750_doubleTFT = 1, /* 36 bit double pixel tft */
21 /* vga channel is not concerned */
139 int channel;/* which channel this crtc stands for*/ member
142 /* below attributes belong to info->fix, their value depends on specific adaptor*/
164 int *channel; member
166 * which channel these outputs linked with,for sm750:
167 * *channel=0 means primary channel
168 * *channel=1 means secondary channel
169 * output->channel ==> &crtc->channel
|
| /linux-6.12.1/drivers/ptp/ |
| D | ptp_idt82p33.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
64 /* Workaround for TOD-to-output alignment issue */
67 /* double dco mode */
87 struct idt82p33_channel channel[MAX_PHC_PLL]; member
94 /* Remember the ptp channel to report extts */
|
| /linux-6.12.1/Documentation/arch/arm/stm32/ |
| D | stm32-dma-mdma-chaining.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
49 STM32 DMA has a circular Double Buffer Mode (DBM). At each end of transaction
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
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| /linux-6.12.1/include/sound/ac97/ |
| D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+
33 /* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
44 /* range 0x3c-0x58 - MODEM */
59 /* range 0x5a-0x7b - Vendor Specific */
62 /* range 0x60-0x6f (page 1) - extended codec registers */
85 #define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */
88 #define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */
93 #define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */
96 #define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */
99 #define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */
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| /linux-6.12.1/drivers/dma/stm32/ |
| D | stm32-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
16 #include <linux/dma-mapping.h>
31 #include "../virt-dma.h"
49 * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits;
65 #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */
66 #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */
158 * struct stm32_dma_cfg - STM32 DMA custom configuration
159 * @channel_id: channel ID
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| /linux-6.12.1/drivers/net/ethernet/freescale/ |
| D | fec_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0
94 * fec_ptp_read - read raw cycle counter (to be used by time counter)
107 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
111 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
114 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
120 * @enable: enable the channel pps output
122 * This function enble the PPS ouput on the timer channel.
131 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
133 if (fep->pps_enable == enable) { in fec_ptp_enable_pps()
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| /linux-6.12.1/include/linux/ |
| D | edac.h | 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
110 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
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| /linux-6.12.1/drivers/gpu/ipu-v3/ |
| D | ipu-image-convert.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2016 Mentor Graphics Inc.
9 #include <linux/dma-mapping.h>
12 #include <video/imx-ipu-image-convert.h>
14 #include "ipu-prv.h"
29 * the DMA channel's parameter memory!). IDMA double-buffering is used
30 * to convert each tile back-to-back when possible (see note below
36 * +---------+-----+
37 * +-----+---+ | A | B |
39 * +-----+---+ --> +---------+-----+
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| /linux-6.12.1/sound/firewire/digi00x/ |
| D | amdtp-dot.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * amdtp-dot.c - a part of driver for Digidesign Digi 002/003 family
5 * Copyright (c) 2014-2015 Takashi Sakamoto
15 /* 'Clock-based rate control mode' is just supported. */
34 * The double-oh-three algorithm was discovered by Robin Gareus and Damien
35 * Zammit in 2012, with reverse-engineering for Digi 003 Rack.
53 * double-oh-three look up table
55 * @param idx index byte (audio-sample data) 0x00..0xff
56 * @param off channel offset shift
66 * of the last non-zero data in dot_scrt()
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| /linux-6.12.1/Documentation/userspace-api/media/rc/ |
| D | rc-tables.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
30 .. flat-table:: IR default keymapping
31 :header-rows: 0
32 :stub-columns: 0
36 - .. row 1
38 - Key code
40 - Meaning
42 - Key examples on IR
44 - .. row 2
46 - **Numeric keys**
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| /linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_cmm.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Color Management Module
27 * @lut: 1D-LUT state
28 * @lut.enabled: 1D-LUT enabled flag
37 return ioread32(rcmm->base + reg); in rcar_cmm_read()
42 iowrite32(data, rcmm->base + reg); in rcar_cmm_write()
46 * rcar_cmm_lut_write() - Scale the DRM LUT table entries to hardware precision
66 * rcar_cmm_setup() - Configure the CMM unit
71 * disabling and programming of the 1-D LUT unit is supported.
78 * TODO: Add support for LUT double buffer operations to avoid updating the
[all …]
|