Decode (full) in projects: linux-6.12.1

Searched full:decode (Results 1 – 25 of 1167) sorted by relevance

/linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwell/
D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 …Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops ro… 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 52 …he number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 57 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 62 … the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 72 …Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also m… 82 …Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also m… 87 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 92 …ycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellx/
D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 …Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops ro… 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 52 …he number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 57 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 62 … the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 72 …Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also m… 82 …Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also m… 87 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 92 …ycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellde/
D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 …Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops ro… 47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 52 …he number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 57 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 62 … the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 72 …Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also m… 82 …Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also m… 87 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 92 …ycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/skylakex/
D	frontend.json	15 "EventName": "DECODE.LCP", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses be… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops ro… 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 58 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 261 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …ber of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/skylake/
D	frontend.json	15 "EventName": "DECODE.LCP", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses be… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops ro… 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 58 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 261 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …ber of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/cascadelakex/
D	frontend.json	15 "EventName": "DECODE.LCP", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses be… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops ro… 46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 58 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 261 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is… 303 …ber of cycles 4 or more uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/ivytown/
D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 30 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 106 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 111 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 116 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 125 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 134 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/ivybridge/
D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 30 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 106 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 111 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 116 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 125 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 134 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", [all …]
/linux-6.12.1/tools/power/cpupower/debug/i386/
D	Makefile	`15 $(OUTPUT)centrino-decode: centrino-decode.c 16 $(CC) $(CFLAGS) -o $@ centrino-decode.c 24 $(OUTPUT)powernow-k8-decode: powernow-k8-decode.c 25 $(CC) $(CFLAGS) -o $@ powernow-k8-decode.c 27 all: $(OUTPUT)centrino-decode $(OUTPUT)dump_psb $(OUTPUT)intel_gsic $(OUTPUT)powernow-k8-decode 30 rm -rf $(OUTPUT)centrino-decode 33 rm -rf $(OUTPUT)powernow-k8-decode 37 $(INSTALL) $(OUTPUT)centrino-decode $(DESTDIR)${bindir} 38 $(INSTALL) $(OUTPUT)powernow-k8-decode $(DESTDIR)${bindir}`
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sandybridge/
D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …ded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excl… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 114 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 122 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/jaketown/
D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …ded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excl… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 114 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 122 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", [all …]
/linux-6.12.1/tools/power/cpupower/debug/x86_64/
D	Makefile	`15 $(OUTPUT)centrino-decode: ../i386/centrino-decode.c 18 $(OUTPUT)powernow-k8-decode: ../i386/powernow-k8-decode.c 21 all: $(OUTPUT)centrino-decode $(OUTPUT)powernow-k8-decode 24 rm -rf $(OUTPUT)centrino-decode $(OUTPUT)powernow-k8-decode 28 $(INSTALL) $(OUTPUT)centrino-decode $(DESTDIR)${bindir} 29 $(INSTALL) $(OUTPUT)powernow-k8-decode $(DESTDIR)${bindir}`
/linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/
D	frontend.json	15 "EventName": "DECODE.LCP", 24 "EventName": "DECODE.MS_BUSY", 33 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 57 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 69 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 304 …re a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at … 328 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 333 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 343 … optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode S… 348 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/haswellx/
D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 93 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 102 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 111 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 121 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 130 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 139 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 148 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while … [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/haswell/
D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 93 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream… 102 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 111 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 121 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 130 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 139 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 148 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while … [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/meteorlake/
D	frontend.json	26 "EventName": "DECODE.LCP", 36 "EventName": "DECODE.MS_BUSY", 46 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 72 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 85 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 354 …re a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at … 381 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 386 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 397 … optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode S… 403 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/rocketlake/
D	frontend.json	15 "EventName": "DECODE.LCP", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 36 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 48 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 60 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 249 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 285 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 299 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 304 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/icelake/
D	frontend.json	15 "EventName": "DECODE.LCP", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 36 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 48 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 60 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 249 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 285 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 299 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 304 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/tigerlake/
D	frontend.json	15 "EventName": "DECODE.LCP", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 36 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 48 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 60 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 249 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 285 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 299 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 304 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/emeraldrapids/
D	frontend.json	15 "EventName": "DECODE.LCP", 24 "EventName": "DECODE.MS_BUSY", 33 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 45 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 57 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 268 …re a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at … 292 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 297 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 307 … optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode S… 312 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	frontend.json	15 "EventName": "DECODE.LCP", 24 "EventName": "DECODE.MS_BUSY", 33 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 45 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 57 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 268 …re a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at … 292 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 297 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 307 … optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode S… 312 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/icelakex/
D	frontend.json	15 "EventName": "DECODE.LCP", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 36 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 48 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 60 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 249 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 285 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at … 299 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 304 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… [all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/alderlake/
D	frontend.json	26 "EventName": "DECODE.LCP", 36 "EventName": "DECODE.MS_BUSY", 46 …n": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instr… 59 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 72 …ption": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e.… 321 …re a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at … 348 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 353 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre… 364 … optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode S… 370 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/ivsrcid/vcn/
D	irqsrcs_vcn_4_0.h	31 #define VCN_4_0__SRCID__JPEG_DECODE 153 // 0x99 JRBC Decode interrupt 33 #define VCN_4_0__SRCID__JPEG1_DECODE 149 // 0x95 JRBC1 Decode interrupt 34 #define VCN_4_0__SRCID__JPEG2_DECODE VCN_4_0__SRCID__JPEG_ENCODE//0x97 JRBC2 Decode interrupt 35 #define VCN_4_0__SRCID__JPEG3_DECODE 171 // 0xab JRBC3 Decode interrupt 36 #define VCN_4_0__SRCID__JPEG4_DECODE 172 // 0xac JRBC4 Decode interrupt 37 #define VCN_4_0__SRCID__JPEG5_DECODE 173 // 0xad JRBC5 Decode interrupt 38 #define VCN_4_0__SRCID__JPEG6_DECODE 174 // 0xae JRBC6 Decode interrupt 39 #define VCN_4_0__SRCID__JPEG7_DECODE 175 // 0xaf JRBC7 Decode interrupt
/linux-6.12.1/arch/x86/pci/
D	intel_mid_pci.c	108 unsigned long decode; in pci_device_update_fixed() local 113 /* Turn the size into a decode pattern for the sizing code */ in pci_device_update_fixed() 115 decode = size - 1; in pci_device_update_fixed() 116 decode \|= decode >> 1; in pci_device_update_fixed() 117 decode \|= decode >> 2; in pci_device_update_fixed() 118 decode \|= decode >> 4; in pci_device_update_fixed() 119 decode \|= decode >> 8; in pci_device_update_fixed() 120 decode \|= decode >> 16; in pci_device_update_fixed() 121 decode++; in pci_device_update_fixed() 122 decode = ~(decode - 1); in pci_device_update_fixed() [all …]

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