| /linux-6.12.1/drivers/mmc/host/ |
| D | dw_mmc-exynos.c | 248 u32 dqs, strobe; in dw_mci_exynos_config_hs400() local
262 dqs = priv->saved_dqs_en; in dw_mci_exynos_config_hs400()
266 dqs |= DATA_STROBE_EN; in dw_mci_exynos_config_hs400()
269 dqs &= 0xffffff00; in dw_mci_exynos_config_hs400()
271 dqs &= ~DATA_STROBE_EN; in dw_mci_exynos_config_hs400()
274 mci_writel(host, HS400_DQS_EN, dqs); in dw_mci_exynos_config_hs400()
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr2-timings.yaml | 35 DQS output data access time from CK_t/CK_c in pico seconds.
40 DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
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| D | jedec,lpddr3.yaml | 59 DQS output data access time from CK_t/CK_c in terms of number of clock
|
| /linux-6.12.1/fs/xfs/ |
| D | xfs_trans_dquot.c | 90 oqa = otp->t_dqinfo->dqs[j]; in xfs_trans_dup_dqinfo()
91 nqa = ntp->t_dqinfo->dqs[j]; in xfs_trans_dup_dqinfo()
268 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_USR]; in xfs_trans_get_dqtrx()
271 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_GRP]; in xfs_trans_get_dqtrx()
274 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_PRJ]; in xfs_trans_get_dqtrx()
486 qa = tp->t_dqinfo->dqs[j]; in xfs_trans_apply_dquot_deltas()
652 qa = tp->t_dqinfo->dqs[j]; in xfs_trans_unreserve_and_mod_dquots()
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| D | xfs_qm.h | 61 xfs_filblks_t qi_dqchunklen; /* # BBs in a chunk of dqs */
141 struct xfs_dqtrx dqs[XFS_QM_TRANS_DQTYPES][XFS_QM_TRANS_MAXDQS]; member
|
| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 163 (including DQS/DQ/DM line) drive strength.
211 (including DQS/DQ/DM line) drive strength.
242 DQS/DQ line strength in ohms.
274 (including DQS/DQ/DM line) drive strength.
|
| /linux-6.12.1/Documentation/devicetree/bindings/mmc/ |
| D | nvidia,tegra20-sdhci.yaml | 100 The DQS trim values are only used on controllers which support HS400
108 nvidia,dqs-trim:
109 description: Specify DQS trim value for HS400 timing.
|
| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ |
| D | ali_drw.json | 297 "BriefDescription": "A DQS Oscillator MPC command to DRAM.",
304 "BriefDescription": "A DQS Oscillator MRR command to DRAM.",
|
| /linux-6.12.1/include/linux/mtd/ |
| D | rawnand.h | 507 * @tDQSCK_min: Start of the access window of DQS from CLK
508 * @tDQSCK_max: End of the access window of DQS from CLK
509 * @tDQSD_min: Min W/R_n low to DQS/DQ driven by device
510 * @tDQSD_max: Max W/R_n low to DQS/DQ driven by device
511 * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
512 * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
514 * @tDSC_min: DQS cycle time
|
| /linux-6.12.1/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1751-xm016-dc2.dts | 378 mux-dqs {
383 conf-dqs {
|
| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx93-tqma9352.dtsi | 55 * no DQS, RXCLKSRC internal loop back, max 66 MHz
|
| /linux-6.12.1/drivers/memory/tegra/ |
| D | tegra210-emc-cc-r21021.c | 100 int dqs = (dev); \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
|
| /linux-6.12.1/drivers/media/pci/cx18/ |
| D | cx18-firmware.c | 334 /* Initialize DQS pad time */ in cx18_init_memory()
|
| /linux-6.12.1/drivers/pinctrl/sunxi/ |
| D | pinctrl-sun9i-a80.c | 242 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
253 SUNXI_FUNCTION(0x3, "nand0_b")), /* DQS */
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| D | pinctrl-sun6i-a31.c | 430 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
862 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
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| D | pinctrl-sun8i-a33.c | 152 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
| D | pinctrl-sun8i-h3.c | 230 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
| D | pinctrl-sun8i-a83t.c | 170 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
| D | pinctrl-sun50i-h5.c | 235 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
| D | pinctrl-sun8i-a23.c | 192 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
| D | pinctrl-sun50i-h6.c | 182 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| D | pinctrl-sun50i-a100.c | 169 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
| /linux-6.12.1/drivers/spi/ |
| D | spi-cadence-xspi.c | 37 /* PHY DQS timing register */
501 "Incorrect DQS pulses detected\n"); in cdns_xspi_check_command_status()
|
| /linux-6.12.1/arch/m68k/coldfire/ |
| D | m53xx.c | 538 /* wait for DQS logic to relock */ in clock_pll()
|
| /linux-6.12.1/arch/arm/boot/dts/nvidia/ |
| D | tegra30-colibri.dtsi | 632 gmi-dqs-pi2 {
|